Subject: VHDL OVL Library and Accellera OVL Meeting Feb 12
From: Harry Foster (harry@verplex.com)
Date: Tue Feb 05 2002 - 12:50:38 PST
Hi Group,
Attached is the VHDL version of the OVL we discussed during our December
Accellera Assertion meeting. The new combined Verilog and VHDL
documentation will be sent out this Friday. A lot of work has gone into
running regressions on the VHDL library to ensure it is consistent with the
Verilog version.
Our next meeting of the Accellera Assertion Committee (OVL portion) is
scheduled for Tuesday February 12-th at 9:00am Pacific Time. The access
information is as follows:
Date: Tuesday February 12, 2000
Time: 9:00am PT.
Domestic Dial-In #: 888-621-9228
Intl Dial-In #: 212-485-8161
Room #: *9724231659*
As was discussed during our December meeting, the VHDL OVL library is in the
process of being donated to Accellera (like the Verilog counterpart). We
can discuss the library during our upcoming meeting.
In addition, I want to discuss my new assert_set assertion to be added to
the future OVL and a few other potential assertion suggestions I've received
from OVL users.
Tom will schedule a separate Accellera Assertion Committee meeting soon to
discuss the Super Verilog assertion extensions.
Best regards,
-Harry
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