Subject: OVL Committee mtg tomorrow
From: John Emmitt (johne@verplex.com)
Date: Mon Dec 10 2001 - 16:41:18 PST
All,
This is a reminder that we have an OVL committee mtg tomorrow at 10am PST. Call info is as follows:
Domestic Dial-In #: 888-621-9536
Intl Dial-In #: 212-364-2900
Room #: *8377539*
The agenda of this mtg is:
1. Review new assertion candidates and other changes (see summary below).
2. Vote on changes and additions to the OVL for the December 2001 (year-end) release.
3. Discuss efforts for standardization of the December version of the library in Accellera.
4. Review latest suggested changes to the OVL concerning definitions of severity levels. (Sean Smith)
------------------------------------------
The set of new assertions in the provisional version of the library:
assert_always_on_edge
Continuously monitors a test_expr at every specified edge of the
sampling event and positive edge of the clock. It ensures that a
specified Verilog expression will always evaluate TRUE on the
edge of a sampling event.
assert_cycle_sequence
Ensures that a sequence of events occurs in the order specified.
(cycle bounded by the number of events specified)
assert_next
Ensures that a specified event occurs after a specified number of
clock cycles. In logical terms, where X denotes the next cycle
operator, "start_event => X^n (test_expr)"
assert_width
Continuously monitors a test_expr. When the test_expr evaluates
TRUE, the assertion ensures that the test_expr remains TRUE
for a specified minimum number of clock cycles and does not exceed
a maximum number of clock cycles.
Other changes/additions:
Header file: ovl_task.h
- contains 3 new tasks: ovl_error, ovl_finish, ovl_init_msg
In addition, the assert_one_hot and assert_one_cold assertions have been re-written to greatly improve their simulation performance.
Regards,
John Emmitt
OVL Committee Chair
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