Subject: Follow-up from meeting
From: Tom Anderson (tla@0-in.com)
Date: Fri Dec 07 2001 - 17:57:41 PST
Since I did a lot of waving red and yellow flags around at
today's meeting, let me explain my concerns. I believe that
any assertion library is somewhat arbitrary, with overlapping
and missing functionality. That statement is probably true of
all libraries; if they were complete then they wouldn't grow
but in fact libraries inevitably grow and change other time.
So that's why I have strongly resisted the early suggestions
to lock the OVL assertion set into the System Verilog language
itself. It's nothing against OVL; you'll note that 0-In has
not proposed our own library as a standard to be added to the
language either. We believe that a simple assertion construct
is far more appropriate for inclusion in System Verilog than
any set of library calls.
Why do I bring this up when no one is currently suggesting adding
OVL assertions to the language? Because I think that adding a
set of temporal constructs that can "express everything in OVL"
when combined with a simple assertion construct is also a very
slippery slope. Just in the little bit of brainstorming that we
did in the meeting, I think I heard at least a dozen "must have"
forms of temporal constructs mentioned. So I worry about adding
a lot of complexity to the language to support every possible
form of assertion "without having to write an FSM."
Personally, I'd prefer that we specify temporal constructs within
assertion constructs as a recommendation and not as an absolute
requirement for System Verilog. But making this a requirement
should draw out some interesting proposals for constructs and
syntax; I look forward to seeing these.
Thanks for your openness to my opinions in the meeting today; I
would be glad to respond to any questions or comments either on
the reflector or sent to me personally. Thanks!
Tom A.
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