Subject: RE: Thursday's Assertion Committee mtg
From: Vassilios.Gerousis@Infineon.Com
Date: Wed Nov 14 2001 - 09:04:24 PST
Hi,
As we discussed in the HDL+ committee, we must follow a process and the timeline as
was stated. The deliverables, expected from the assertion committee are:
1- OVL: Library and SRM.
2- Assertion for Verilog (applied to both IEEE 2001 and SystemVerilog): My discussions with different vendors at DAC 2001 and also with users, this seems to be the direction that many have indicated as a preference.
So please try to help to move in this direction. We have a committed timeline and milestones. Help to make it happen.
Best Regards
Vassilios
-----Original Message-----
From: Harry Foster [mailto:harry@verplex.com]
Sent: Wednesday, November 14, 2001 4:33 PM
To: Simon Davidmann; John Emmitt; assertion@eda.org
Cc: Harry Foster; Tom Fitzpatrick
Subject: RE: Thursday's Assertion Committee mtg
One more thing--keep in mind that the assertion construct language
requirements are really only defined in section 4.1 (which is only 1.5
pages). Nothing else in the document that I sent out is a requirement.
Hence, I believe unless we want to open up these requirements to something
bigger--then we should be able to reach consensus on the simple assertion
construct.
Best regards,
-Harry
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