Subject: RE: Thursday's Assertion Committee mtg
From: Simon Davidmann (simond@co-design.com)
Date: Wed Nov 14 2001 - 07:44:14 PST
yes my suggestion would be next Tuesday sometime.
and yes I think we need to do 2 meeting in Dec and plan to have
requirements fully reviewed and voted on by the end of the year - so we can
be ready to start reviewing syntax in the new year.
Simon
At 07:23 AM 11/14/2001, Harry Foster wrote:
>That would work for me since I can't attend this weeks meeting. If we have
>any hope of making the HDL+ scdhedule of showing an implementation within
>the January timeframe we need to get moving on this NOW! If the committee
>is committeed to this goal then we will need to have more than 1 meeting a
>month in December. I believe it is achievable since really the minimum we
>need is a simple assert construct added to the Verilog language that is safe
>in simulation (i.e., no false firings). Anything else is nice but not
>necessary.
>
>Best regards,
>
>-Harry
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