RE: Verilog++ Assertion Extension Proposal

Subject: RE: Verilog++ Assertion Extension Proposal
From: Harry Foster (foster@rsn.hp.com)
Date: Wed Aug 15 2001 - 06:33:40 PDT

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Here's the attachment I neglected to send out yesterday. What has changed
in this version of the proposal is section 4.1 (a few additional
requirements) and section 4.2 (introduce two simple assertion constructs as
one possible form of assertion specification).

-Harry

• application/pdf attachment: AssReq.pdf

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