Subject: Verilog++ Assertion Extension Proposal
From: Harry Foster (foster@rsn.hp.com)
Date: Tue Aug 14 2001 - 16:12:00 PDT
Attached is the latest version of the strawman assertion requirements
proposal. This document should not be considered the official Accellera
Verilog++ Assertion Extension Requirements Document. The intent of this
document is to propose a set of requirements that should be considered when
creating the final Assertion Requirements Document. In addition, this
document does not set any requirements on assertion implementation or
syntax. My intent is to use this document to focus our discussions while we
create the "real" requirements document.
We can discuss this document at this Friday's Assertion meeting. John will
send out access information concerning this meeting soon.
Best regards,
-Harry
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