After ten years of standardization, VHDL continues to revolutionize electronics design by helping in the description of portable, accurate models for simulation, analysis, documentation, and synthesis. As dictated by IEEE rules, the VHDL standard requires reballoting by the end of 1998. This provides an opportunity to reconsider the strengths and weaknesses of VHDL and to determine the future of the language and its role in the development of electronic systems. One area identified as critical to current and future development of electronic systems, hardware/software codesign, pertains to the concurrent development of hardware and software system components throughout the design effort. This paper investigates, from the perspective of hardware/software codesign, the requirements for VHDL in 1998 (and beyond) to help identify what changes are needed. We include with the requirements the rationale for each.
The analog extensions to VHDL 1076 developed under IEEE PAR 1076.1 will be brought to ballot in 1997. There have been a number of presentations in other venues focusing on the application of the extended language. In contrast, this paper presents the rationale for the design of the language extension itself.
This paper reviews proposals for object-oriented extensions to VHDL and places them within a taxonomy based on the modeling requirements they address. The paper also presents a detailed discussion of issues to be considered in adding object-oriented extensions to VHDL, including concurrency, abstraction using entity interfaces, signal assignment semantics, shared variables, multiple inheritance, genericity and synthesis. Emphasis is placed on the importance of designing simple orthogonal semantic mechanisms that interact in well defined ways, and that integrate cleanly with existing language features.
This paper presents the concurrent and distributed implementation of a VHDL Design Manager. Emphasis is put on the three main roles as Integrated Common Database, Design Data and Process Manager, and the three main capabilities: Workspace management, Version and Configuration Management and Design Process control. Current VHDL-ICE version implements only the first of these capabilities. For this reason it is described in more detail than the others. Future papers will deal with next VHDL-ICE versions.
We have worked on VHDL design processes for the past 5 years on a variety of projects, from large satellite signal processing payloads and avionics image processing systems to performance level modeling systems. During this time we have continued to refine the components of the design process. In this paper, we show how we applied our design process to the 1996 VIUF VHDL Design Contest. We credit this process to our entry winning the industry competition. We will describe our process, the metrics we collected and the information we learned from the metric data.
The OMI tool/model interface developed by the Open Model Forum (OMF) uses the concept of a "model manager". In its most general form, a model manager acts as an interfacing agent between a tool and a set of models that are used by that tool. In this paper we explore the role of a model manager in OMI model delivery and examine two possible model manager scenarios as detailed examples. The OMI interface is described in a companion paper.
Any system is potentially subject to multiple objectives and no single model will be able to capture all the objectives of the system. To deal with multiple objectives, we have to create and manage multiple models of the system each covering certain aspects. Each aspect represents a level of abstraction for the system. We present the concept of abstraction networks, a formalism for multilevel hierarchical systems. Abstraction networks are constructed by applying abstraction mechanisms to existing models and organizing them hierarchically. They comprise various representations of a system at different levels of abstraction. The concept of abstraction networks and its extension by VHDL is applied to a FIFO. Further, a knowledge-based framework which supports the process of modeling and simulation based on abstraction networks is specified. An important rationale of the framework is to capture simulation related issues such as simulation efficiency and model complexity.
The VITAL 95 standard for VHDL libraries was written primarily to solve the problem of developing consistent ASIC libraries with VHDL. This paper discusses how a design methodology for board design with board-level simulation models written in VITAL can be advantageous, and outlines lessons-learned at TRW over the past couple of years in implementing board-level component libraries in VITAL/VHDL. The most notable advantage of developing board-level simulation models in VHDL is the seamless simulation environment when integrating board-level simulations with both behavioral simulations (systems level simulations) and FPGA and ASIC simulations assuming they are VHDL-based. There is a considerable advantage from eliminating the twin nuisances of supporting and training on multiple simulation tools, and verifying and maintaining the translations of designs and test vectors or test fixtures between those disparate simulation environments. In order to arrive at the goal of a seamless simulation environment, some technical issues had to be addressed and solved. Working primarily with high-speed boards, we had to apply VITAL modeling to families of ECL and GaAs components which have some unique modeling considerations - such as differential signals and intermediate logic level (not 0 or 1) inputs. We sought to keep our "schemato-centric" approach to design - since the schematic is the database from which the product (printed circuit board) is designed, and most board design engineers are more comfortable with schematics than with large structural VHDL netlists. We therefore had to integrate our VITAL models with the hierarchical and structured design methodologies of our Cadence and Mentor schematic capture tools. A long term problem in maintaining component libraries is their sheer size. Total component counts in the tens of thousands of components are not uncommon for a typical design development organization. Since many components use the same simulation model except for the timing data, we sought to reduce the component count by reusing simulation models, separating out the timing completely by utilizing the VITAL standard's SDF backannotation capabilities. We've achieved a working method for technology independent libraries using SGML-based timing files which are parsed by a software program which writes out an SDF file for the design according to the timing selections made by the designer. Other board-level modeling topics discussed in this paper include: the viability of writing large MSI models to strict VITAL level 1 compliance, and modeling passive components in VHDL (especially bi-directional resistor modeling).
VDFL is a specification language developed to describe DSP systems. Since the design of DSP systems is moving to higher levels of abstraction, VDFL allows DSP systems to be specified at a higher level of abstraction. The VDFL specification is translated into floating-point and fixed-point VHDL models for system simulation. This allows finite wordlength effects to be investigated. VDFL is also translated into a signal flow graph, for input to a behavioral synthesis tool. As the design moves towards implementation, the VDFL model can be used to validate lower level VHDL models. An example is presented and extensions for multirate systems and sequential constructs are discussed.
This paper explores the challenges for system-level design modeling and verification and examines the applicability of VHDL to them. Fundamental issues are raised in which VHDL currently falls short of addressing these challenges in an effective way. Among these are interprocess communication semantics, evolution of design blocks through the design process, distinction between system function from system architecture, and the separation of behavior and communication. We then explore language requirements for addressing these challenges. Implications on VHDL and, in particular, on a potential evolution of the language are raised. Finally, we conclude on recommended future paths for VHDL.
Making executable specifications is one approach for dealing with the still dramatically increasing complexity of digital systems. A lot of effort is spent world wide for the definition of a new, or selection or extension of an already existing, language. We analyze in that context the re-standardized Ada'95 language and compare it to VHDL. First language capabilities are compared. Strong emphasis is also taken on performance aspects, which are important for exhaustive system evaluation. To do so, we related both languages in a set of benchmarks to C, which is said to be the fastest higher level language.
We present our approach to the definition of a multi-paradigm environment to specify, model and synthesize embedded DSP systems. Instead of assuming one semantic ( for instance, synchonous semantics [15] ) to specify and model the whole system, we propose to use simultaneously several semantics to describe and validate key system properties. Traceability of system requirements is challenging with such an approach. We propose an architectural view of systems which defines components and connectors to support respectively functional and non-functional requirements modeled with specific semantics. Using the object-oriented framework Ptolemy [13] , which supports simulating and prototyping of heterogeneous systems, a global view of the system is ensured, allowing us to validate its behavior.
The Continuous Electronics Enhancements using Simulatable Specifications (CEENSS) program, begun in 1995, has the following major objectives: Define a Methodology for the design of board/module-level electronic products employing Simulatable Specifications to significantly improve development productivity and cost. Specify the form of Simulatable Specifications such that they are tool/vendor neutral and foster development of CAD tools supporting their use. Define Modeling Guidelines for the creation of Simulatable Specifications. Demonstrate the application of this Methodology to commercial and military design tasks. Transition this Methodology and Simulatable Specification definition into the design community.
This paper describes STEVE, a syntax-directed editor for VHDL, which uses auto-completion and automatic template insertion to accelerate the entry of syntactically correct VHDL models. It is part of a larger project, VIDE, which integrates textual and graphical tools for HDL design entry. STEVE extends the SAVANT intermediate representation to deal with representation of templates and the on-screen presentation of a VHDL model. STEVE demonstrates the advantages of SAVANT's extensible object-oriented structure, and shows how it facilitates the integration of a new tool into an existing CAD tool framework.