The two major Hardware Description Languages are Verilog and VHDL. Both languages allow high-level and gate-level descriptions. Verilog has been generally supported by ASIC vendors at the gate-level for sign-off simulation; whereas, VHDL is used mainly for system design at behavioral and RTL levels. With the introduction of VITAL specifications, using VHDL for gate-level simulation has become effective. This paper examines the features of Verilog and VITAL gate models. The structure and character of modeling in the two environments are presented. Furthermore, the different descriptions on modeling for timing violation handling, state table usage, output assignment, edge sensitive delay, back-annotation, and other factors are discussed along with the examples. The strategy is targeted at the sign-off quality of VITAL model generation.
The hardware description language (HDL) wars tried to make us all pick a side and then come out fighting. Time, the true test, has shown that both VHDL and Verilog are here to stay. Both languages are being used successfully in real world designs today-sometimes even together. Where does each language shine? Where do their limitations start to show? What is it like to use them together? These and other question are briefly answered from the perspective of a designer who has used VHDL and Verilog both separately and together.
In past work the need for mixed language simulation environment to meet the needs of todays designers has been made clear [1], and several areas of potential conflict between the two languages have been illustrated including time-scale resolution, type mapping, and synchronization. This paper concentrates on the issue of resolving conflicts in the semantics of the simulation cycle between Verilog and VHDL to provide a well defined synchronization mechanism that ensures predictable event scheduling as simulation activity passes across the language interface. This work is based on research being done at Cadence to resolve semantic issues for a mixed language simulator currently under development. The paper shows how the native code approach to simulator implementation allows a feasible solution to the problem of mixed language semantic resolution.
There is a need for formal verification techniques in hardware system design. This requires a formal interpretation of VHDL is the language most used by designers to describe and synthesize electronic systems. The formal model proposed is based on Coloured Petri Nets and can cover all aspects of the language. The starting point is the interactive processes executable model of the language. The formal model of a description includes the specification in Petri Net terms of a model consisting of the user-defined processes resulting from the elaboration of a VHDL description, the kernel process (simulator) and the communicating links between them.
The paper discusses issues related to the application of information modelling to VHDL'93. It is shown that an information model of VHDL can provide a uniform description of VHDL objects at different levels of design and of the behavioural semantics of the language. This enhances the application range of the model and its coverage of the language.
Various mechanisms have been investigated for producing a formal definition of VHDL. This paper will explore yet another: Communicating Sequential Processes, or CSP. This formalism has some advantages, both for VHDL in general, and in defining the relationship between a VHDL model, a WAVES dataset that specifies the test vectors for the model, and a tester specification.
The need for a high quality validation suite has been an issue since the very first VHDL standardization meeting held in March 1986. While several attempts have been made, there is still not in existence a sufficient suite of tests that is complete enough for VHDL-1987, much less VHDL-1993. The last attempt at a validation suite was by VI with the development of a partial VHDL-1987 suite, produced under contract by The VHDL Technology Group. After the development of the suite, VIUF decided that the magnitude of the project was beyond the means of the organization. In November of 1994, in behalf of DoD the USAF Wright Laboratory signed a Memorandum of Agreement with VIUF to complete the development of a Validation Suite under joint sponsorship. This paper will discuss the status of the current suite and plans for the development of an extensible high quality validation suite for VHDL-1993.
Benchmarks are often referenced to make engineering tool performance evaluations. Over the past year, several groups have completed benchmarks to quantify the ability of VHDL simulators. Due to the relative immaturity of VHDL, many people are in a learning mode and are creating test cases as a good way to quickly learn about a VHDL tool. Many of the evaluators that have published benchmark information, have had an active history of working with VHDL and are regarded as experts in the VHDL arena. This paper will describe criteria to be considered when developing and reviewing a benchmark: What criteria should one consider when performing or evaluating a benchmark? What is the internal design environment? Internal test results of criteria will be provided. What are limitations in applying results?
The Army is leading a tri-service effort to develop a handbook on using VHDL to document the design of military digital electronic systems. The handbook is designed to assist its audience in tailoring the VHDL Data Item Description for VHDL contract deliverables so as to achieve the maximum benefit for the government at a reasonable cost. This paper presents an overview of the handbook, discusses four major issues that have arisen in developing the handbook that are still not completely resolved, and presents three recommendations made by the handbook for developers of models that are to be delivered to the government.
This paper addresses the problems presented by the introduction of handling exception events in a behavioral VHDL model. The most common exception event is the hardware reset but similar problems and issues are encountered when introducing any asynchronous exceptions like interrupt service requests. It will present various techniques for handling exception events in behavioral VHDL models, using reset as an example, and discuss their respective merits. It then looks at the solution available for behavioral models in Verilog and ADA programs then proposes similar mechanisms for VHDL.
This paper discusses a virtual company concept as part of the RASSP (Rapid Prototyping of Application Specific Signal Processors) program's overall technical objectives. This concept involves the collaboration of distributed design teams utilizing the RASSP Design Methodology. This approach requires close coordination among the development team members, machine independent information management, and company independent resource management. Presented are experiences from the RASSP Demonstration project that used a multicompany, multi-platform approach for developing a VHDL description of an IRST (InfraRed Search and Track) processor.
As part of US Department of Defense's RASSP program and also within the industry, VHDL is finding increasing use in the co-specification, codesign, co-simulation, and verification of embedded hardware/software systems consisting of multiple components (processors, memories, etc.), ASICs, and diverse interconnection and backplane options. Typically, VHDL models of hardware components are used to debug software design and ease integration and test, in what is essentially a hardware-less codesign process called virtual prototyping. Models developed for virtual prototyping provide more information about the components (and their internal state) being modeled than that required by EIA 567. The electronic data sheet of EIA 567 provides pin-based timing, physical, and electrical packages for components, while models used in virtual prototyping provide an augmented electronic data sheet that included so-called virtual pins that probe internal state for purposes of system design and test (but are not included in the component's manufactured form). This paper proposes a systematic and consice draft standard for models used in system-level synthesis and simulation that augments EIA 567 to include virtual views within an augmented electronic data sheet. This draft proposal also establishes the levels of fidelity required for VHDL models for electronic design and simulation at multiple levels of abstraction. The model developer can also use this proposal to convey the level of fidelity incorporated into a model facilitating documentation and interoperability.
Prototyping is an old technique commonly used to develop systems in general and electronic systems in particular. However, the use of VHDL for developing the hardware part of these systems allows the introduction of a new aspect of prototyping based on extending the common use of a VHDL simulator. This approach allows to use a virtual hardware model able to interact with the software of the system and even with other parts of it, such as the mechanical ones, emerging what can be considered a new technique that we named VHDL Virtual prototyping. The paper presents the evolution of this technique throughout its application in several TGI projects: IDeASG, ECUO and SIMAIDC.
Significant increases in system complexity, shorter time to market requirements, rising lifecycle costs, and requirements for rapid upgrades of embedded signal processor systems together with agile system redesign (adaptibility) to multiple mission and threat scenarios, are motivating the development of new methodologies for rapid prototyping of systems (i.e., system synthesis) as part of the US Department of Defense's RASSP program. One methodology, that is the subject of this paper, involves the use of virtual prototyping to rapidly design hardware and software and facilitate their integration and test. This paper describes various aspects of the virtual prototyping process, starting with the VHDL library development of commonly used COTS processors, then proceeding to the modeling and prototyping of multiprocessor systems, and finally the virtual prototyping of an Infrared Search and Track (IRST) system prototype developed in collaboration with the Lockheed Sanders', Hughes', and Motorola RASSP demonstration teams. This paper will attempt to document our experiences with virtual prototyping of complex digital systems, such as radar signal processors, consisting of a few hundred processors with computational complexity rated at 1-100 GFLOPs, processing real-time image data at 100-1000s Mbytes per second. Our main result shows that virtual prototyping reduced the in-cycle time required for hardware/software integration and test from 10-24 months typically required for large-scale designs to less than 2 months (assuming that all model libraries were designed and validated off-cycle). It was also observed that virtual prototypes that model a 200-processor signal processor to a high-level of fidelity (e.g., clock-edge behavior) demand very high computational resources (a potential show-stopper), and efficient mechanisms that trade-off fidelity (e.g., mixed-level) for performance need to be investigated.
Automatic VHDL static analysis can be a valuable approach to develop, measure and compare models generated by hardware designers or by high-level specification tools. Moreover VHDL code should be developed according to some well founded guidelines to improve the quality of the overall design process. Goal of this paper is to summarize the activities carried out within the SAVE project, leading to the development of a collection of static analysis tools in order to reduce the time spent in the design verification phase, to improve modifiability, reusability and readability of models and to manage hardware semantics. SAVE activities include theoretical analysis tasks as well as practical experimentation and implementation of prototypes tools.
The generation of testbenches for complicated VHDL models is a labor intensive task rivaling that of generating the model itself. What is required is a high level approach to test bench development which relieves the modeler of the details of this process. In this paper, methods employing CASE tools, design tools and model libraries are described, which allow the modeler to develop testbenches at a high level of abstraction and thus reduce the amount of labor required for testbench development.
This paper outlines and provides an example approach to developing a standard WAVES test bench for VHDL model verification. Issues regarding the use of WAVES in a VHDL simulation environment will be discussed. This includes how and where to obtain the WAVES standard packages, setting up the WAVES_STD library, and compiling the WAVES standard packages with the VHDL model. Next, an example of a self monitoring WAVES test bench is presented and discussed. Finally, simulation efficiency issues and some conclusions are discussed.
This paper describes a generic WAVES compatible VHDL testbench that has been developed to produce test vector information that includes variable length cycles and strobe times. The test vector formats are compatible for translation to several Automatic Test Systems (ATSs) for test. The testbench is created automatically using a tool developed by the IIT Research Institute Reliability Analysis Center (IITRI/RAC) and the Rome Laboratory (RL). The tool parses a VHDL structural model and generates the testbench. The testbench uses stimulus/response data captured in the IEEE Standard 1029.1, Waveform And Vector Exchange Specification (WAVES), format. The tool was developed as part of an actual project designed to demonstrate the use of VHDL and WAVES for board-level test program set (TPS) development. A case example for an actual board model is presented. Details are also provided on the demonstration project and on specific processes that were required to make the testbench WAVES compatible. The advantages of using the WAVES format and future plans are also addressed.
While VHDL is a powerful tool for the design and verification of digital electronics, this power is accompanied by great language complexity. This complexity can only be reduced by the use of intelligent tools capable of watching the design as it evolves, catching errors and speeding input. This paper describes the development of such a tool, a structure editor for VHDL.
This paper describes a new tool box for editing VHDL and generating AST. It is integrated in the ASAR multi-formalism framework oriented towards Architectural Synthesis and generates a common intermediate data-flow format GC, for the different formalisms and tools available in that framework.
It is well known that VHDL synthesis systems do not accept the complete IEEE Std 1076-1987/1993. The intention of this paper is to learn about the necessity of synthesis guidelines, or more precise their irrelevance. Most VHDL users are familiar with the problem that a given synthesisable VHDL description for synthesis system X is probably not accepted by synthesis system Y. For reasoning about a VHDL description an intermediate format based on single token graphs is used. This intermediate language, that is developed in the ESPRIT SPRITE Project 2260, is called SIL: Sprite Input Language [KL92]. It is not the intention to show how the complete VHDL language is translated to SIL. A simple example is used to show that different VHDL descriptions with the same behaviour will indeed result in the same SIL graph, hence in the same hardware. The mapping of a SIL graph to hardware is outside the scope of this paper.
Built in self test (BIST) has been used for testability of digital systems. VHDL modeling of BIST, not only can evaluate circuit under design for its testability, it can also be used for top-down design verification. This paper describes a VHDL modeling strategy for register level description of BIST. We will show how a BIST architecture inserted into a top level design can become useful in the lower level implementation of upper level components of a design. The paper will show application of the technique develop to a simple RISC architecture.
A new RAM BIST (Built-In Self Test) methodology is described which provides a high quality at-speed, distributed test solution, Tests can be run at full speed, with multiple unrelated clocks, covering multiple RAM blocks, and to target different RAM topologies. The method suits modern ASICS with multiple RAM blocks and multiple clocks. The implemented BIST is capable of running at the full system speed, and it is in many ways superior to previous solutions for in-system testing or production testing. To develop the BIST generators, the author used an iterative prototyping method. As described in this paper, programs were written to automate the development process.
VHDL gate level models for fault simulation by the Critical Path Tracing method have been developed. These models are used by a VHDL test bench for pseudo random test generation. Modeling strategy and the test environment will be described in this paper.
A top-down VHDL design environment was developed to design a digital signal processor for a space application. VHDL was used for the entire design from behavioral simulation through the physical or structural register transfer level, RTL, descriptions. A unique built-in test approach used VHDL to design all test circuitry thereby enabling full gate array ASIC simulation via VHDL prior to synthesis. Custom SRAMs were also added to the gate array VHDL library to provide dense on chip memory.
Virtual prototyping is a VHDL technique for validating a hardware and software design before hardware is developed. A virtual prototype was used with great success in the Rapid Prototyping of Application Specific Signal Processors (RASSP) program for the development of an Infrared Search and Track (IRST) processing system. This paper describes the RASSP virtual prototype and test results achieved by the demonstration team.
This paper describes a research project, carried out by Bournemouth University in collaboration with IBM Havant UK, for a possible extension to VHDL. This paper demonstrates how an object-oriented approach applied to VHDL will increase the designer's productivity using the three concepts of objects, classes and methods. Finally, a proposed object oriented extension to VHDL will be examined, which can handle Encapsulation, Abstraction and Derivation.
To allow the rapid prototyping of application specific signal processors, an extensive VHDL library of architectural building blocks is needed. In this paper, we describe an object-oriented approach to generating a library of VHDL synthesizable models. A hierarchical classification of digital component attributes is described, with examples for integer adders. A model generation methodology, using 'C' preprocessor directives, is also described. We conclude with an example of the VHDL code generated for a 4-bit ripple carry adder, and its synthesized schematic.
This paper proposes a VHDL integer package as a candidate for a new VHDL companion standard.
This paper presents our experience for merging analog and digital architectures under an existing Very High Speed Integrated Circuit Hardware Description Language (VHDL) design environment. Three major areas are presented: a brief description of a mixed-mode architecture, the incorporation of analog into the traditional digital VHDL design flow, and the mixed-mode ASIC simulation. Finally, an overview is presented of the need for a standard hardware description language with modeling capabilities for the full analog domain.