As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. We present a methodology and tool for system-level specification, design and refinement, based on VHDL, that results in an executable specification for each system component. The specification for each component can then be synthesized into hardware or compiled to software. We highlight advantages of the proposed methodology compared to current practice.
This paper presents an automatic test bench generation system for VHDL behavioral models. Modeler's Assistant, an interactive CAD tool developed at Virginia Tech, gives the graphical representation of a VHDL behavioral model, called a Process Model Graph (PMG). The Process Test Generator (PTG) is used to generate the stimulus/response test sets for individual processes of a PMG. The Hierarchical Behavioral Test Generator (HBTG) accepts the PMG and the test sets produced by PTG as inputs, and then hierarchically constructs a test sequence for the entire model. The test sequence is converted into a test bench by the Test Bench Generator (TBG), and it is then used for simulation of the model. Experimental results show that the test benches generated exercise the models thoroughly.
In the area of digital system test, fault collapsing is referred to the process of reducing faults in a circuit to only those that can be distinguished. In local fault collapsing, one fault is selected from each of the equivalent fault classes of logical gates. The selection will be based on the connections made to the ports of a gate. We have developed VHDL gate models for local equivalent fault collapsing. This paper presents a VHDL based test environment that uses fault collapsing VHDL models to generate a list of faults for test generation and fault simulation. Our VHDL modeling strategy and examples will be discussed.
STD_LOGIC_1164 values let a VHDL user represent known and unknown signal values based on two levels (0 and 1) and three strengths. This paper formalizes a two-part level/strength model for STD_LOGIC_1164 values to develop strength-related transformations that can be used in synthesis. We represent unknowns as a set of choices among possible well-defined ("real") values. This lets us formally define "implementation" as the process of narrowing the set of choices. Defining "strong equivalence" (levels and strengths) and "weak equivalence" (levels only) then allows one to determine, for example, under what conditions "or/and" logic can be considered (logically) equivalent to a bus with weak and high-impedance drivers. The formalism is used to study the composition of resolution functions, and to compare them to equivalent hardware implementations.
A systematic hierarchical partitioning algorithm for high-level VHDL descriptions is proposed. The partitioning algorithm is based on quadrisection. Major contributions of this paper include exploiting VHDL hierarchy for local expansion of VHDL entities and extension of regular quadrisection to three-stage hierarchical operation. At each hierarchical level, the complexity of our algorithm is linear in the number of nets. The results show that our hierarchical algorithm provides solutions better than min-cut and compatible with the flat quadrisection. Keywords: VHDL, High-level Design, Partitioning, Quadrisection.
This paper describes the techniques employed in the development of a VHDL-based system simulation of the Honeywell RH32 Prototype Development Unit (PDU). The architecture of the PDU is briefly described, and a design process is presented. The system simulation approach is discussed, including simulation model types, their development and validation, and testbench structure. Additionally, techniques for performance measurement and analysis of the simulation results are discussed, which can be used to improve the system design at the chip and board levels. Finally, conclusions drawn from this effort are presented, along with indications of future work to be performed.
VMS (A VHDL Modeling System) is a tool which automates the model generation of ASIC gate level cells for VHDL logic simulators. VMS is a rule based system and has built into it the expertise of model developers in the form of rules. VMS handles many of the complex and intricate model behavior and is a high productivity tool.
Many commercial CAE tools that are available to circuit and system designers only support a subset of the modeling levels needed to specify, analyze, design and verify digital signal processing systems. This restricts verification efforts as the design moves top-down from algorithm definition to hardware implementation. This paper describes a design environment that allows the designer to move through and mix different modeling levels and addresses the specific concerns of an IC solution. The modeling flexibility of VHDL serves as the foundation of this environment. The paper also includes an application example.
Flexible, hierarchical test benches are developed naturally as part of the normal model development process and support VHDL, WAVES, and company-proprietary standards. The integration of these tool-automated VHDL test benches is described.
This paper examines techniques for developing VHDL descriptions of recursive hardware structures, using recursive and repetitive component instantiations. A fat tree interconnection network is examined as an example of a recursive hardware structure. The recursive description is easier to develop, and more clearly express the structure, making it easier to understand. The main difficulty in developing repetitive structures lies in devising a way of inter-connecting the basic components comprising the structure. It is shown that the difficulties result from fundamental language design decisions made in VHDL, and that it is not appropriate to modify the language to avoid the difficulties. Hence, in general, the recursive style is preferred over the repetitive style for describing recursive hardware structures.
In this paper, we discuss bringing two early stages of digital system design-operational specification modeling and performance modeling- under the same simulation environment. This unification is possible by integrating the operational specification model and the performance model for a given system under design, so that the two models can be simultaneously simulated and analyzed in a synergistic manner. Such an integration enables a novel design methodology that makes specification modeling an integral part of the design process.
Automation of the Hardware/Software Codesign methodology brings with it the need to develop sophisticated high-level synthesis tools. This paper presents a tool which is the result of such development. This tool converts standard C code into an equivalent VHDL behavioural description. This description is used to generate a chip-level hardware interconnect of identical functionality to the original C code.
The UVA uninterpreted modeling methodology uses a set of predefined primitive elements to model computer systems that can be used to explore different design alternatives. In this paper, we present an overview of the VHDL perspective of our UVA design methodology. We present Colored Petri Net models for the primitive elements that formalizes the UVA methodology. We then present a translation algorithm which translates the Petri Net (PN) model to VHDL so that the PN model can be simulated. In order to speed up the simulation, we also present a set of reduction rules that reduces the complexity of the PN model.
This paper describes the use of VHDL in the specification, design, and development of a large-scale project that includes several custom ASICs, standard digital components, board-level design, and bus interfacing. The common mechanism for the design was the use of VHDL in system testing, behavioral descriptions, structural descriptions, and synthesis. The use of VHDL allowed the project to be completed in one-fifth of the time used for previous methods.
We describe design decisions made while testing and debugging our behavioral VHDL model of the Intel i960 MX processor. The model provides human readable representations of processor information, to simplify debugging and documentation. An interactive simulation, using an X window interface, aids in debugging the VHDL model and application software. We developed an automated result checking entity to verify instruction operation tests and a flexible method to generate chebyshev approximations of transcendental functions and check their results.
During the last few years HDLs have become the driver behind the move to top down design in the electronic design industry. Two HDLs, VHDL and Verilog HDL have become the dominant de facto industry standard HDLs. Since the industry has made a hugh investment in both HDLs and there is every indication that each will retain significant market share for the foreseeable future, it is critical that there exist a standard methodology for interoperability between the two languages. This paper describes the relevant issues for interoperability and suggests solutions where they currently exist. It further summarizes the work which needs to be done for a complete solution and the groups who are involved in achieving this goal. Please note that the emphasis in this paper is on simulation since the semantics of the two languages are specified only for that discipline. 'While the importance of other disciplines such as logic synthesis cannot be underestimated in the top down design process, the lack of standard language semantics makes general analysis problematic.
This paper shows the main results after the experience of building tools for VHDL applications using some commercial VHDL front-ends. To this purpose we have evaluated several VHDL analyzers for performance, compliance and application support. This work has been done in order to implement tools based in a formal model of VHDL. We stress the necessity of a safe way to comply with the standard avoiding cumbersome interpretations.
We present a high level synthesis framework which guides the designer in devising design methodologies. The framework supports backtracking and parallel exploration of alternative methodologies. Encoded knowledge assists the designer in selecting methodologies and tools, while designers retain control during the synthesis process. The framework facilitates maintainability and extendibility as new tools and methodologies are developed.
Database support for VLSI CAD is proposed to facilitate data sharing and tool interoperability. A methodology for database development that can utilize standard specification languages and formats is described here. The methodology is applied to developing a database language for the structural semantics of VHDL (described in EXPRESS). This research provides a foundation for developing semantic mappings between information models and for integrating VHDL design management with database technology.
We are convinced that a universal VHDL gate library for ASIC sign-off simulation can be developed, though the optimized VHDL code for various target simulators may differ. Our solution is based on VHDL models written with a unique entity declaration and various architecture bodies targeted at simulators. We concentrate here on VITAL compliant architectures as VITAL should soon become a standard.