The Multicomponent Synthesis System (MSS) is a vertically integrated collection of design Synthesis tools for top-down design of multichip modules (MCMs) from behavioral specifications. MSS consists of a high-level synthesis subsystem, a partitioning engine, a collection of structural silicon compilers, a test structure compiler, a test-bench compiler, a packaging compiler, and various component libraries and technology files. A typical design flow through MSS begins with a behavioral specification in VHDL and a performance specification in terms of area and clock-speed of the digital system to be implemented. The specification is then processed by the various tools in MSS. MSS is a VHDL-centered design environment. MSS blends synthesis and simulation tools operating at various levels of abstraction to quickly design correct application-specific MCMs. Functional test bench compilation is used as the primary means of achieving this goal. This paper discusses the various synthesis and test algorithms used in MSS and their interaction. Through a small example we show how the designer can steer the design process to generate an application-specific MCM design.
VHDL enables designers to describe their designs in a technology independent format allowing reusability and a smooth migration from one technology to another. To fully realize the benefits of designing with such a methodology, standards need to exist by which component specifications and performance figures may be unambiguously determined and communicated from one technology to another. The establishment of IEEE standard 1164 as a medium for describing the logic states of circuit elements is an example of the type of uniformity that is required. Currently, no standards exist for calculating delays through circuit elements. Each ASIC vendor will most likely have its own set of equations for calculating the delays and timing parameters of their cell libraries. Each vendor will most likely use equations and parameters that will model the actual physical delays in varying amounts of detail. Furthermore, the same parameters are known by different names or have different interpretations. This results in the need for customized packages to handle the requirements of each vendor. If a circuit board is to contain parts from different vendors and they frequently do, a simulation of the board would be a very onerous task requiring the smooth integration of various packages and possibly numerous conversion functions. A universal timing package providing the necessary functions would eliminate such problems. By placing such functions in a package, it is possible for every model to access them and thus guarantee a consistent method of deriving timing data. This paper discusses the need for, and benefits of, such a timing package. Some guidelines for developing the package are also given. Finally, a sample package implementation is shown.
A popular software property, that of interactiveness, is brought to the realm of hardware models. Through interactive testbenches a model developer can provide a more flexible environment in which to exercise his model and gain a quicker and better confidence in its correctness. Through interactive interfaces to the models themselves, users unfamiliar with the model or the modeling language used can run and control a simulation, monitoring the information that is of interest. This approach to modelling and testing is illustrated by several actual examples as well as the tools facilitating the development of interactive models and testbenches are presented.
In traditional bottom-up design complex units are built up in a recursive process from simpler ones, starting with gates of a library. Therefore during the whole design process the speed and area of a unit are precisely known. This is not the case in top-down design, where many realisation parameters are fixed late in the design process. Therefore the efficiency of top-down design is increased significantly by generic design, where each entity is parameterised persistently. In a design project with three different ASICs, VHDL modeling guidelines for generic design have been established. These modeling guidelines are discussed using a subdesign from the design project. An organisation scheme for the design data supporting generic design is described. The limitations of such a generic design at different levels of abstraction are indicated. The implications of generic design to design reusability and future system development environments are discussed as well.
The management of VHDL model complexity and related evaluation of VHDL model parameters at the behavioral level is of interest as a mechanism in system performance analysis. This paper addresses the use of Petri Net models and applications for performance analysis of behavioral level VHDL designs. Performance analysis relies on a class of model views that simplify through the abstraction of selectively (un)interpreting model information [1]. For VHDL, one uninterpreted model view can be defined by analyzing only the control structure information in the model architecture and where most computational and datapath information is not utilized. The uninterpreted model retains the necessary timing and sequential information needed to analyze the system performance and complexity of the design with significantly reduced computational overhead. One of the primary mechanisms for expressing uninterpreted models is through the formalism of Petri Net theory. This paper expands on previous work on performance analysis [2] for structured programs by addressing Petri Net modeling and the statistical structures associated with VHDL statements used in RTL and behavioral modeling. The creation of Petri Net representations from VHDL models appears to be a useful and appropriate mechanism for analyzing attributes of VHDL models such as information paths and complexity of model behavior. Petri Nets have been used in the evaluation of design complexity measures of related modeling areas [3, 7]. Petri Nets (PN) and VHDL share several characteristics, including data concurrency and hierarchy, that facilitate modeling of design complexity and information. The paper is organized into two parts. First, it is shown how a VHDL model's statements can be represented using a PN. Second, two applications of a Petri Net representation of a VHDL model are discussed. A complexity measure for a VHDL model based on the reachability concept of Petri Nets is explored through a method of determining simple data paths and loops in the PN representation; This measure provides information that can be used for verifying bounds of a behavioral VHDL model's testability. A method of using the probabilistic delay information of a Timed Petri Net is then demonstrated as an approach to estimating critical path timing of a behavioral model.
The VHISIC Hardware Description Language(VHDL) is a formal notation intended for use in all phases of design of electronic systems and has become an accepted standard[1]. While much progress has been made in formulating the language, and making this standard more adaptable to the needs of the microsystem design community, the language does not directly address issues relating to VHDL model verification and test. Unfortunately, the manual generation of a stand-alone, design specific VHDL test environment that would enable the model verification process as a function of the model development cycle can be as labor intensive and time consuming as the development of the model itself. Consequently, the task of testbench generation is often viewed as a peripheral task, something to be tacked onto (rather than integrated into) the model development process. This paper presents a highly configurable automatic VHDL testbench generation methodology (Testview) in support of VHDL model verification and test at any level and phase of the modeling process. Innovative features of this integrated VHDL testbench methodology include: support of abstract data types at the I/O boundary library management of testbench architectural components and user interface modules dynamic generation of user interface for support of testbench options and parameters
Successful ASIC design and fabrication depends on the application of highly accurate yet efficient gate-level logic simulation. The cost of developing sign-off quality macro-cell libraries is quite high; the use of a standard modeling language such as VHDL is regarded as a way of eliminating the need to construct a library for each proprietary simulator that an ASIC vendor supports. However, the current version of VHDL does not adequately address all of the modeling requirements of gate-level simulation. Additionally, proprietary gate-level simulators still exhibit significantly better performance and capacity than today's fastest VHDL engines. This paper surveys the requirements of accurate gate-level simulation and assesses the ability of VHDL to support those requirements. A set of benchmark data is presented which demonstrates the current performance and capacity gap between VHDL and dedicated gate-level simulators. Finally, some language change requests are proposed which specifically address gate-level deficiencies based on analyzing the execution profile of several VHDL simulations.
VHDL High-level description is useful to describe the behavior of circuits with abstractions at their early development stages. Software VHDL simulators are, however, not adequately fast for large circuits. Logic synthesis can be applied to obtain gate level description from VHDL description so that gate-level logic simulation machines can be used. However, since only fairly low level conventional logic synthesis can be treated, high-level descriptions have to be written down to this level. We developed a method to obtain gate-level descriptions from high-level behavioral description. Each gate of the description represents a control and data flow node of a high-level behavioral description. We estimated the simulation speed of high-level descriptions employing simulation machines, and found that it is accelerated 400 times over software simulators.
This paper describes how VHDL has been used to create a behavioral-level model for the analysis of Futurebus+ based system architectures. The goals of the effort are presented as a backdrop for the information that follows. An overview of the model design is presented, which includes several modeling and analysis methodology highlights. This is followed by the discussion of an example architectural analysis highlighting the use of pseudo-random distributions and Rate Monotonic Scheduling theory to determine backplane traffic message mixes. The results of the analysis including a Futurebus+ specification issue will be presented.
In today's Air Force, the development of weapon system electronics is both a complicated and integration intensive endeavor. With the advent of Integrated Weapon System Management (IWSM) (i.e., 'cradle to grave' responsibility), proper representation of electronic hardware is crucial for efficient post-production reprocurement. This paper describes how VHDL and a Top Down System Simulation (TDSS) program can provide solutions to the aforementioned challenges.
This paper presents RAPID, a design system that combines graphics and text to support the hardware/software design process. The graphical portion of RAPID allows the designer to represent system components as either rectangular objects or as graphical objects (constructed using xfig) implying some behavioral functionality. Each component can have up to three (equivalent) descriptions: a structural decomposition of its internal components, a hardware description in VHDL, or a program representation in Ada. The system modeler can configure the system with any set of hardware/software bindings. When the selection for the configuration is complete, RAPID drops the software components from the display the modeler then reconnects the remaining hardware components with an embedded processor. Finally, the Ada programs are compiled, RAPID instantiates the proper VHDL design entity/architecture pairs (which must be compiled) and the entire system can then be simulated.
As the necessity for a high percentage of fault-free end products becomes a growing concern, development of better and faster fault simulators has also become a major issue. The speed at which the fault simulation is performed grows in importance as the circuits grow larger. In this paper, we propose a VHDL modeling technique for easy fault insertion and parallel fault simulation. The models require minor modification of non-fault structural models and make it possible to insert faults into a circuit at the deepest levels of nesting without requiring recompilation of the entire circuit for newly introduced faults. The modeling technique also enables us to perform parallel fault. simulation of unlimited faulty circuits. We propose a set of utilities to be used, and a methodology to model circuits for achieving the above.
This paper discusses VHDL switch models that adjust their logic flow direction at the beginning of a simulation run. The timing of such a model depends on the capacitive load at its drain or source terminals, and this timing can change dynamically depending on the visibility of load connected to an output through transmission gates. The usage of these models is primarily in creating an interface between VLSI design tools and high level VHDL design environments.
We have developed a VHDL modeling strategy for modeling Field Programmable Gate Arrays (FPGAs). Different modeling levels have been implemented for Xilinx XC2000 products as well as other series such XC3000 and XC4000. These models can be used for FPGA simulation from LCA file format. This file is used for configuring our programmable models as well as the actual FPGA parts.
This paper presents a graphical methodology for developing and documenting hierarchical VHDL models at all levels of abstraction that include both behavioural and structural elements. The methodology is a modification and refinement of Buhr diagrams developed by Dr. R.J.H. Buhr of Carleton University for describing concurrency in Ada. Because there is a well defined transform between the diagrammatic elements of this methodology and VHDL code, we believe it would lend itself well to automated means of generating VHDL from diagrams and diagrams from VHDL.
This paper describes the issues associated with the development of a system simulation which combines: the needs of Hardware and Software Co-Simulation; the simultaneous use of C and VHDL; the use of (graphical) real-time stimuli; and the use of (graphical) real-time display techniques. The major focus of the paper deals with merging separate versions of time: the time as seen by the hardware (measured in ns or ps); the time as seen by the software (measured in ms or seconds); and the time as seen by the user of the simulation (i.e. the person entering the graphical stimuli and interpreting the graphically displayed simulation results). The paper: defines co-simulation needs; examines the problems associated with the simulation of hardware-software and software-hardware interaction; describes the set of heuristics used to facilitate efficient interaction; and examines techniques to facilitate real-time interaction with the simulation. Resolution of these problems is fundamental to an interactive co-simulation system.
This paper presents a technique used for constraint-driven partitioning of VHDL designs for multicomponent synthesis. Hard constraints (area, clock speed, heat dissipation, and number of structures) on the entire design and on the individual structures (area, clock speed, pin count, and heat dissipation) are satisfied during the process of partitioning. The technique uses a partitioning engine that provides the user with a mix of interactive and numerous automatic partitioning approaches. PDL is used for performance specification and measurement.
This paper presents a system that automatically generates VHDL Models from VLSI layouts provided in transistor netlist format. The generated models can be simulated in available VHDL Simulation Environments and can thus provide an analysis of both logic and temporal behavior. Parameterized behavioral VHDL models have been developed for switch level and gate level components using simple but effective timing models. Program modules for extraction of hierarchical components and for generating from the extracted components, a VHDL structural model with instantiated components have been implemented in PROLOG. Comprehensive results and considerable speedups have been obtained for appreciable performance as compared to general purpose simulation and verification systems like spice and irsim.
VHDL is a convenient language for developing of ASICs using a top down design approach. A methodology addressing good VHDL coding practices and synthesizability requirements is described. Problems encountered and their solutions in using this methodology on an ASIC project are also discussed.
In the Personal Computer marketplace, hardware system designers are faced with the challenge of building differentiating system-level features around more and more complex standard product microprocessor components. Each new generation of the microprocessor spawns a new generation of the motherboards and systems. Success in the marketplace is often driven by time-to-market for these key leading edge products. This paper discusses the motivation for, and the development of, a behavioral VHDL bus functional model (BFM) for the Pentium processor [1], a new high performance, and Intel386/486(TM) compatible microprocessor from Intel corporation.
The use of an object-oriented database to support a visual design environment is presented. ViDEO, the Visual Design Environment with Objects, is based on VHDL, and incorporates both research and commercial VHDL tools. ObjectStore, an object-oriented database management system, serves as the basis for sharing design data between CAD tools. Database support for editing visual designs, compilation of visual designs into textual VHDL models, and simulation of VHDL models is described. An overview of the use of a database for integration of CAD tools into a design environment is presented.
This paper describes our experience developing the methodologies and design management needed to use VHDL as the common simulation language for the design of a DSP chipset. This chipset is the core of a second-generation CCITT H.261 videophone application. Our first requisite in the design process was to determine system and chip partitioning. From there we had to determine which internal and third-party vendor tools to use to design the chipset. A top-down design methodology approach was used on the entire chipset: but because portions of the original design were reused, we also developed various design import methodologies. Finally, in order to facilitate a smooth design flow, we paid close attention to the logistics of design management.
Performance limitations of distributed simulations are due to the target machine, the simulation algorithm and the natural parallelism of the model. In order to build a set of well known benchmarks, we propose here an intrumentation method of VHDL models. This method allows extraction of natural parallelism during a sequential simulation.
VHDL does not allow component overloading of operators, or component instantiation in any function or procedure for that matter. As a result, when synthesizing operators in VHDL that should imply structured logic, a designer has the limited choice between component instantiation in the dataflow, or relying on the default implementation provided by the synthesis tool. This paper presents a methodology that allows VHDL designers to utilize technology specific macros, while maintaining a technology independent design style.
Although the capabilities of VHDL for the definition, modeling and simulation of complex systems are widely admitted, some specific system-level modeling strategies have to be adopted to take advantage of all the power the language can offer. A project where VHDL was used to model a real-life example at behavioral level is presented in this contribution, making a special effort to describe the VHDL style required for such level of abstraction, and focusing on the problems which arose during the encoding of the system in VHDL and on the solutions that were given to these problems.
This paper describes HIDE, a system that automatically generates VHDL and Verilog bus-interface models from a high-level specification of interface behavior. HIDE users need not be familiar with VHDL or Verilog, and instead specify interface behavior using familiar hardware constructs, such as timing diagrams, state diagrams and truth tables. We also introduce a hierarchical model of interface behavior that supports the model-generation task.
Top-Down System Simulation (TDSS) is an effective means of defining, designing and verifying the requirements and capabilities of large/complex electronic systems. TDSS follows top-down analysis and design by allowing models of the system to be developed and simulated during each phase of the product development life cycle. Each model adds detail to the previous one and reflects a non-ambiguous specification of the system throughout the complete product development lifecycle. This document will discuss the use of TDSS in the development of a wireless LAN system. The intention here is to provide the reader with a detailed understanding of the TDSS Methodology using the development of a wireless LAN system, as an example. As such, this document provides examples of the trade-offs and issues associated with applying TDSS to the development of a wireless LAN system.
Due to continuing growth in the complexity of computing applications, the conventional uniprocessor computers often do not provide adequate processing power to obtain a desired system response in an acceptable amount of elapsed time. Parallel processing techniques offer a potential for speed-up in a variety of applications. However, in order to exploit parallel processing techniques for an application of interest, a parallel computing system designer has to correctly make several important decisions such as selection of an appropriate parallel computing platform.
As designs continue to become more complex, the design cycle continues to shorten, and synthesis tools move towards using more abstract descriptions, the importance of including test features in the synthesis process will dramatically increase. This paper describes a VHDL control hardware synthesizer, NUSYN 2.0, which has been modified to synthesize testable designs along with a minimal set of test vectors. The synthesis methodologies are presented along with the generation, compaction and application of the test vectors. Other unique features of NUSYN 2.0 include asynchronous control, multiple active states and the synthesis of a design in CMOS rather than as a netlist. NUSYN 2.0 has been placed in the public domain.
Existing VHDL tools in the marketplace adopt one of two implementation strategies. These implementation approaches are: 1. Pseudo Code: A VHDL model is translated into a stream of data which is interpreted by a a body of code, usually written in C, as a sequence of synthetic instructions. A single common simulator program usually executes all models. 2. C Code: A VHDL model is translated into a C program, which is compiled to produce a module which can be linked with other modules, as well as a support kernel. The resulting program is the simulation. Each separate simulation may imply a unique executable program. Both of these approaches introduce extra layers of representation and indirection which simplify the task of building and porting the simulator, but at the expense of inhibiting VHDL performance from reaching its theoretical maximum. This paper describes a VHDL simulation system based on direct generation of native machine code, which is directly executable by the workstation hardware. This new approach alone immediately and significantly improves simulation performance, especially at the behavioral modeling level. The paper describes the code generation and optimization strategy, which is similar to techniques used on other RISC-targeted compiler/code generators. This paper further outlines a strategy for high performance gate level simulation through the application of a set of methods appropriate for each network determined by analysis of the network during static elaboration. These methods are executable native code sequences which compute the minimum amount of information needed to manage a signal, as a function of the particular signal usage.
In this paper, we present new method for dealing with the measurement of jitter performance for digital system synchronizers. The key to this technique is the creation of a VHDL model for a digital synchronizer at a high (algorithmic) level. The results from VHDL model simulation are analyzed using programs written in C for signal filtering. This simulation technique is aimed at improving the process of optimizing the performance and cost-effectiveness solution of expensive equipment, and the high-level modeling techniques contribute to the system design process.