The use of VHSIC Hardware Description Language (VHDL) as a modeling, simulation, and synthesis tool in an engineering design methodology is presented in this paper. Use of VHDL models can be extended into the verification of specifications, test plans, and test procedures prior to commitment to hardware, fully developed software, and LSI, thereby catching problems earlier in the design cycle. This paper discusses the possible uses of VHDL in various parts of the design cycle, and comments on the viability of using VHDL in design phases.
This paper describes research work in system redesign using VHDL. This research is centered on the redesign of the Remote I/O Module in the SINCGARS Radio [1]. Using VHDL, the behavior of the controller, which currently uses micro-processor, is modeled as a Finite State Machine, FSM. By implementing the FSM as an ASIC chip, the microprocessor could be eliminated. A modeling technique of FSM, in which each state is represented by a single process is presented. The scheme contrasts with other approaches in which whole FSM is represented by a single process and each state is represented by either a case statement or an if statement. Our approach has some advantages such as the modularity of design, state decomposition and availability to easily describe a complicated state. It also has the benefits of separate compilation and individual simulation. When a circuit is implemented by a structural description, it needs to be checked a timing correctness such as hazard and race. Hazard and race condition detection in VHDL, which is one of the critical parts of timing verification, is also presented. Using ternary logic in VHDL, the hazard and critical race condition can be detected. In real hardware gates, gate delays can be varied depending on the environment, such as temperature and fan-out. If a precise gate delay is assigned, a critical race condition can be detected with a high degree of confidence; a false detection may in reality be due to delay varying.
As we look into the future, we see that VHDL modeling for digital simulation will be readily available. Tools will provide capability for creating VHDL models and for interfacing with other tool environments. Today, many tools in support of VHDL are in their infancy. Several interfaces still need to be created, and it will take time to prove that these interfaces and tools are production ready. VHDL tools need to merge and interface with tools that are presently being used to design complex digital circuits in a production environment. The efficiency and support of present tools are key factors in determining the best level of VHDL integration to fit your companys design environment. This paper will attempt to bring to light those nasty questions that many VHDL advocates attempt to avoid when discussing VHDL within a specified methodology. With this information, users will be in a much better position to plan the implementation of VHDL and thereby achieve many of the targeted benefits. To meet increasing demands for shortened design cycles, higher quality and productivity, VHDL must be incorporated into our design environment rather than being avoided!
There has been a profusion of electronic standards in recent years for the design, description, specification, and simulation of electronic hardware systems and sub-systems. Such standards include VHSIC Hardware Description language (VHDL), Waveform and Vector Exchange Specification, (WAVES), Electronic Data Interchange Format (EDIF), and Initial Graphic Exchange Specification (IGES) among others. Although these standards enhance engineering productivity and product integrity, a need still exist for an integrated environment for electronic hardware descriptions and specifications which incorporate these standards. The benefits of such an environment include: technology independent data package descriptions an electronic vs. paper documentation environment user friendly interface for accessing specification information This paper presents an Electronic Technical Data Package (ETDP) methodology for the development of a cohesive EDA framework, required to capture all of the critical data necessary to support engineering redesign functions an requirements at the microsystem level.
This paper outlines our experience from the investigation of the applicability of VHDL to communicate physical properties to and from the logic design and physical design tools. This information transfer is implemented using a combination of VHDL modeling and design methodologies and the present-day tools. The information flow between existing tools is described first and then the impact of the proposed methodology on these tools are discussed. The area of application chosen for this study is board designs using standard off-the-shelf components.
In this paper, we promote the idea of level and domain independence in language-driven hardware synthesis. With design input abstraction shifting towards system levels, the language aspect of synthesis assumes more importance. The underlying synthesis core tools that support it operate in very specific domains, such as Boolean, FSMs, and behavioural control/data flows. These tools need to be domain-specific in order to apply specific algorithms effectively. The onus is on the synthesis language interface to process level and domain information of the input so that the relevant synthesis transformation can be applied. An intelligent interface thus performs a level and domain mapping by serving this information to the appropriate synthesis tool. We believe the most important issue in achieving level and domain independence is that of design representation. Design representational issues deal with intermediate formats and underlying hardware models. Our experience shows that using one unified design representation throughout the synthesis process affords several advantages. We therefore support the call for a standard synthesis intermediate format that embodies the features mentioned in this paper.
Lack of close hardware correspondence in the existing VHDL synthesis subsets results in circuits that are not minimal in terms of gate count and path delays. However, VHDL being a broad language, contains a number of constructs intended for synthesis which are not typically used in synthesis tools today. In this paper, we attempt to narrow the gap between VHDL and hardware by porting the constructs of a Register Transfer synthesis language to VHDL. AHPL (A Hardware Programming Language) is selected for this purpose. In addition to being one of the languages considered in designing VHDL, AHPL has stood the test of time in being a robust synthesis language. Synthesis from the resulting VHDL subset, refered to as VHDLRT, is compared to other methodologies. Moreover, the pitfalls present in the existing subsets are emphasized. Subsequently, the features of AHPL as well as the mapping of AHPL into VHDL are presented.
A VHDL synthesis compiler(Warp) is described which synthesizes multiple finite state machines into a new Programmable Logic Device, the CY7C361. To achieve the concurrency and partitioning of FSMs needed by the user of the CY7C361, a behavioral level synthesis system was created, with VHDL as the entry vehicle. We describe the VHDL models and synthesis operations of the Warp system in this paper
VHDL is a complex language which is difficult to compile. It is often edited and compiled repeatedly, placing strenuous performance requirements on a compiler. This paper describes VCC, a program which distributes the compilation of VHDL across a network of Unix workstations for faster compilation.
This paper proposes a strategy to implement a parallel VHDL simulator for fast simulation on the Connection Machine. The VHDL description for a circuit is translated into an intermediate form for simulation. The intermediate form is simulated with discrete event simulation techniques, such as Time Warp and the Chandy-Misra algorithm, on the Connection Machine. Signal assignment statements in the VHDL description are transformed into gate processors, and component instantiations are handled by their expansion into a combination of basic elements. Experimental results of VHDL simulators with several simulation techniques are given. Compared with the VHDL simulator on the Sun 3/280, the parallel simulator using the Chandy-Misra algorithm on the Connection Machine is much faster by several orders of magnitude.
VHDL, like many other simulation languages, requires acceleration to meet users' changing needs. With evolving applications of the language, the requirements for acceleration will also change. This paper will discuss today's technology and offer direction for future technology development.
Currently, no synthesizer supports the full set of VHDL. The synthesizable VHDL subset varies depending on the synthesizer. Therefore, a designer needs to know the details of the synthesizable VHDL subset and the synthesis policy set by a particular synthesizer. This paper presents a development of VHDL Synthesizability Checker(VSC) which performs a rule-based, configurable VHDL synthesizability checking. It reads a VHDL model, checks the synthesizability of the model, and generates a report. Unlike a checker within a synthesizer, VSC performs the checking process based on a user-defined rule set. By separating the user-defined rule part and the synthesizability checking part, a designer can configure his/her own synthesis rule set, and can handle the different synthesizable VHDL subset.
In order to accurately simulate the logic and timing properties of a custom designed circuit layout, behavioral CMOS transistor models were written using the VHSIC Hardware Description Language (VHDL). A simple netlist translator program maps the layout netlist to an equivalent transistor level VHDL architecture which can be directly simulated, either as a standalone component or as a system module. Simple VHDL constructs and existing delay models were used to develop the transistor models that provide the design engineer with accurate circuit timing and logic information for simulation with higher level models.
As VHDL becomes more popular and gets coupled with behavioral synthesis, the question of integrating the immense design data bases built around schematic capture, preserving the investments already made into traditional design methodologies, and utilizing them to the best of one's advantage become of paramount importance in a transition environment. To address some of these important questions, we present HDLsmith, a VHDL code generator. In addition to making it possible to recapture existing designs in a pure behavioral model, HDLsmith makes existing designs compliant with MIL-STD 454L. The generated code can be used for accelerating functional design verification, and as a basis for formal verification against a functional specification.
Computer simulation has become an indispensable tool in the design of VLSI circuits. Traditionally, a number of levels ranging from high-level behavioral to low-level electrical description have been successfully used to model and simulate digital circuits. In the past, modeling and simulation of analog circuits were restricted to the electrical or transistor level description, although this level is CPU-time consuming. More recently, however, an emerging need for the simultaneous representation of electronic circuits (analog or digital) at more than one level of description has spurred an intense research effort in multi-level modeling and simulation. Mixed-mode simulation i.e. simulation which simultaneously combines analog and digital descriptions, has been particularly prominent in this fast evolution. For the digital domain, VHDL is a powerful and now widely accepted standard (for both modeling and simulation). There is also an urgent need for analog designers to have a standardized modeling and simulation language. Despite the major differences in concept between analog and digital modeling, a unified modeling capability seems to be possible especially at the behavioral level of abstraction. In this paper we discuss the different concepts of analog and digital modeling, and the requirements needed to describe both in a unified mixed-signal modeling language. The results of this work are preliminary ideas about future analog feature in VHDL (AHDL for Analog Hardware Description Language or VHDL-A).
This paper proposes a file format for timing information which can be back annotated into a VHDL design. The authors are in the process of establishing an IEEE PAR for, among other issues, standardizing such a format and this paper gives an overview of a strawman for that effort. The file format is based on the SDF format for Verilog with modifications to make it appropriate for both VHDL and Verilog models. The proposal targets the 1992 version of the language which is currently under development. The proposal covers back annotation of timing information appropriate for commonly used model characteristics such as pin to pin delays, wire delays.
This paper describes the implementation of IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, using behavioral VHDL (VHSIC Hardware Description Language). The IEEE 1149.1 standard provides a structured method for implementing testability in circuit designs and may be used to provide many different levels of testability. By implementing IEEE Std 1149.1-1990 in VHDL, designs which use the standard may be constructed and simulated to determine the operation of the design and the effectiveness of the included testability. This paper describes the basic components of IEEE 1149.1 as well as the test bench used to stimulate the finished logic. The test bench includes low-level and high-level functions which ease the test application process, provide high-level control, and are portable between different implementations of the test logic. An example which employs the test logic and uses the test bench functions for test application is included.
During the development of the Waveform and Vector Exchange Specification (WAVES), the additional need for an exchange format for fault information was recognized. As a result, IEEE PAR 1029.2, Fault Dictionary Language (FDL) was born. This paper discusses the development that has been performed to this point on FDL, including the requirements and guidelines that will shape the development of the standard. These requirements and guidelines have been formulated during the IEEE DASS Test Analysis and Standardization Group working meetings. Usage scenarios for the standard are presented to further demonstrate the intent of the standard. In addition, the organization of the data to be represented in FDL will be examined, and the impact of the "lessons learned" during the WAVES implementation process on the FDL implementation will be discussed. Finally, possible implementations of FDL based on VHDL will be presented.
This paper presents an approach for verifying the temporal sequencing of VHDL behavioral models. The goal is to verify that the control flow of a behavioral description satisfies of the behavioral specifications, described in a formalism based on reified temporal logics and on a notion of activity.
High-level synthesis is a mature research area with a high industrial potential and high-level systems are seen to be an emerging key technology in digital design. VHDL, being standard, may facilitate the acceptance of these new CAD tools. Although VHDL is a very rich and powerful description language at the RT and logic levels, it presents some limitations when it is used at high level. In this paper a description is given of the high-level simulator SiVa. It accepts the same VHDL descriptions and the same semantics as PSAL2, the high-level synthesis tool developed at our department, thus overcoming the problems caused by using a logic simulator at the high level. High-level simulation represents a first step in the development of multi-level simulators to cover all levels from high to logic level.
This paper presents a study on obtaining high level behavioral models that have accurate timing behavior. The primary concentration is on Finite State Machines (FSM), and we will use timing information from gate-level implementation of these state machines to back-annotate the high level models. The implementation of Mealy and Moore machines is studied, and encoded state assignments versus one-hot state assignments for these machines are compared. Feasibility of timing back annotation of high level FSM descriptions with the information obtained from gate level is analyzed.
This paper presents approaches for the evaluation of VHDL simulators that are straightforward to apply. Performance indices are outlined by which a simulator - and other VHDL tools - may be evaluated. Two types of benchmarks, simple synthetic and composite synthetic, are defined. These are the cornerstones in the evaluation scheme that was developed. The structure, requirements, and considerations in the use of these benchmarks are also given. Means are proposed to reduce the effects of some of the factors that can cause variations in simulator evaluation results. A description of some of the benchmarks that were developed to validate the evaluation methodology is presented. Finally, sample results are given and discussed. For the evaluation scheme that was developed, the principal parameter of interest is execution time.
Conventional logic simulators calculate node logic and delay values in separate processes. The delay value is used for scheduling the logic value on the node. In this paper we will present the Timed Logic Simulation (TLS) method, which allows us to combine logic and delay computation processes into one process. In addition to a faster simulation, using this method a netlist can be converted into a set of Boolean expressions, containing detailed timing and logic information. VHDL implementation of this method allows extracting functional models from netlist descriptions, the simulation accuracy of which is identical to netlist simulation.
Object Oriented programming languages contain a number of capabilities that are very useful in designing and building large systems. Some of these include encapsulation, reusability, inheritance, and message passing. This paper will describe some of these techniques, give a brief description of their relevance to large system design, and show how they can be applied to VHDL descriptions.
This paper discusses modeling techniques that can be employed by designers to model network behavior. The techniques can be used to implement a wide range of network behaviors ranging from pre-layout signal delays to complex system-level queuing models.
This paper presents Statecharts as a graphical entry for automatic generation of synthesizable VHDL descriptions. Using a concrete example, the process of creating the Statechart model is shown, along with the VHDL description and the circuit that was automatically generated from the Statecharts. This paper also demonstrates the superiority of Statecharts over Communicating State Machines in terms of clarity, compactness of the description and compactness of the resulting circuit.
This paper will discuss VHDL modeling techniques for programmable logic design and a suite of translation tools developed for the automated generation of VHDL models from some typical programmable logic design formats. The application of PLD VHDL models to systems level integration in VHDL design automation environments will also be addressed.
This paper describes the design and implementation of an automated VHDL model and testbench generator within an ASIC design environment. This capability allows a designer to generate a behavioral and/or gate-level VHDL description of a design by exploiting the environment's high-level function generators. This description can then be exported to a commercial VHDL environment for simulation and/or synthesis. The testbench provides automated functional verification.
In [DON] P. Beauvillard from Cadence Design Systems says : "Even if it were possible to design a complex ASIC at the gate level, statistics show that about half the time it won't work when interfaced to the rest of the system. It's imperative to simulate performance at a high level of abstraction. You need an HDL to do this". This is quite true, that is why the development of rapid prototyping environments working from a behavioral specification including genericity and abstract data types [WHI, BIF] is important. The methodology we use is inspired by the Balzer's model, used in software engineering [BAL]. As it is illustrated by Figure 1. the user will be able to simulate his description at each phases of the synthesis process and refine his specifications depending on the results of the simulation. This paper will describe the first phase of this project : the implementation of genericity and abstract data types in VHDL, the inclusion of VHDL in the interactive programming environment generator : Centaur, and the generation of full behavioral VHDL from generic VHDL.
One of the current challenges in the design of digital systems is the transition from specification to hardware. Major advances in the development of requirement analysis tools in recent years have aided this transition. These advances coupled with the advent of logic synthesis tools have provided a strong foundation for development of a seamless, requirements driven design methodology that ensures specification compliance across all levels of design abstraction. A methodology has been developed at Raytheon to ensure design integrity from specification to hardware implementation for the development of both Field Programmable Gate Arrays (FPGAs) and ASICs. This paper addresses the development of this methodology, which relies on the use of i-Logix's EXPRESS VHDL as the front end requirements analysis tool. Automatic generation of synthesizable RTL VHDL from EXPRESS VHDL's statechart notation enables the exploration of multiple synthesis paths. This paper addresses the exploration of these multiple synthesis paths and the various CAE tools, such as Synopsys, Exemplar, Xilinx, and Mentor, used to achieve the automatic generation of logic.