The Hughes Defense Communications' Electronic Design Automation (EDA) support group has actively tracked and participated in the development of VHDL from its early days. Information on the language and the resultant impact on design methodologies was regularly disseminated to the ASIC/FPGA user community. Various training paradigms were used over the years to bring users to an effective mastery of VHDL. The training paradigm continues to change as we move to utilize our internal internet pages for interactive one-on-one training. This paper will review the paradigms used, the effectiveness and findings of each, and lay a course for future training experiences.
Simulation time is a crucial bottleneck in the design process. In many cases a simulation is run several times with different inputs. Making such simulation runs parallel will significantly reduce the simulation time. In this paper we are introducing a concurrent simulation implemented with standard VHDL'93 to optimize simulation time of RTL level models.
Due to the great complexity of VHDL models that are created today, the amount of CPU time required to simulate these models and the amount of labor required to develop these models have become critical issues. The amount of CPU time required to simulate a model can be directly influenced by the efficient use of VHDL concepts in creating the model. Research in the determination of what VHDL concepts and modeling styles are most efficient will be discussed in this paper. The development of tests that can be run on VHDL models to reveal the efficiency of the code in the form of a numerical efficiency rating will also be discussed.
Comprehensive and affordable evaluation of the fidelity with which a VHDL tool implementation and VHDL language specification correspond is the focus of this research. The research is embodied in a practical semi-automated validation tool, VIVA. Previous work in this area focused on hundreds to thousands of manually written test cases (and potentially expected result files). Such suites were expensive to develop, expensive to maintain, and often conferred less than optimal language coverage due to practical limitations on the available development resources. Research and development efforts described in this paper utilize several, comparatively terse adaptations of a language specification to drive a semi-automatic test suite generator and eventually a VHDL tool under test. Specification files derived from the language specification express lexical, syntactic, semantic and temporal properties of a concurrent, imperative language. The language being specified may include both intrinsic functionality (such as IEEE Std. 1076-93 [1]) and extrinsic functionality (such as the standard logic packages defined by IEEE Std. 1164 [2]) Manually-supplied tuning parameters guide the validation suite generator as it emits a stream of VHDL test files, expected results and derivative information used to facilitate human analysis of failed tests. Tests evaluate both a tool's ability to process correct input and a tool's ability to discriminate errors in the input stream. Whereas VIVA's primary focus is validation of tools implementing VHDL-related standards, preliminary analysis suggests that the techniques are extensible to support validation of other concurrent, imperative languages such as Ada. Temporal validation of constraint-based languages, such as the proposed VHDL-AMS extensions to VHDL, may require further work.
As part of the ARPA RASSP1 program, Mississippi State University (MSU) has developed and released a VHDL model for the Xilinx X4000 FPGA families. The Xilinx X4000 family is a static RAM based FPGA. The basic logic cell is called a Configurable Logic Block (CLB) and contains two 4-input lookup tables, two D flip-flops, and dedicated carry logic. IO is handled via a versatile Input Output Block (IOB). There are several other logic resources on the chip as well - an on-chip oscillator, fast decoders, tri-state buffers, pullups, high drive buffers, startup logic, and boundary scan capability. The current release of the model supports all logic functionality except for boundary scan and startup logic (work is in progress in this area). Timing functionality of all blocks is supported; package and speed grade specific timing information is read from Xilinx-generated data files. The additional functionality provided by the X4000E family in the form of synchronous SRAM blocks is also included. A VHDL structural model is generated via a Perl5 script from the LCA (Logic Cell Array) netlist file which is created as part of the normal development cycle. The LCA file can include back annotated net delays which are incorporated into the generated model. The VHDL structural model is composed of the primitive components found on the Xilinx X4000 FPGA - Configurable Logic Blocks, Input-Output blocks, internal oscillator, etc. The X4000 module library has been tested with both Mentor Quick-VHDL and Vantage VHDL development environments. The X4000 VHDL model is available via the WWW; the LCA to VHDL model generator script is available for remote execution via the WWW.
In this paper, we describe a totally integrated FPGA development platform, which very effectively provides the means for design, verification, testing, and system integration of reconfigurable logic designs based on the latest in FPGA technology. This unique integrated system concept makes complete the development cycle for a reconfigurable FPGA signal processor design, by merging in a seamless fashion, the capabilities of custom-developed design automation methodologies with conventional EDA Tools and a unique real-time reconfigurable FPGA hardware platform. This flexible board architecture represents a precise duplication of an optimized FPGA processing element architecture. This is contrasted to typical commercial FPGA development platforms, in which the hardware does not represent the actual architecture or allow operation at the clock speed of the target design. VHDL is used extensively throughout the system. In fact, the common and essential link in the integrated system is use of VHDL-based EDA-tools throughout, which allows implementation of an end to end testing, verification, and system integration concept.
Critical timing path in a logical circuit is the longest sensitizable path from primary inputs to primary outputs. Finding sensitizable paths is achieved by eliminating false paths. This paper presents VHDL simulation models for finding false paths. The algorithm used and VHDL modeling strategy will be discussed.
This paper presents a model for characterizing delay and power for CMOS logic cells that accounts for input slope and output capacitance loading. A method for deriving the model parameters and VHDL modeling for simple logic gates is presented. The model makes feasible delay and power estimation at VHDL simulation speed, the errors of the model prediction are less than 5% of Spice results.
As ASIC designs become larger and more complex, the functional verification environments (the testbenches) must become more comprehensive in scope if they are to provide the basis for adequate validation and verification of the designs. This does not mean, however, that the testbench must itself become more complex or that it becomes harder to use. This paper presents details for using VHDL Signals in a unique way to simplify and ease communication between different components of a testbench, and provide versatility to users of the environment when generating test vectors.
This paper introduces a DOD-developed computer program which transforms a VHDL model, associated stimulus/response vectors and boundary data sheet information into a VHDL deliverable which satisfies key elements of the government VHDL Data Item Description (DID), DI-EGDS-80811. The computer program, developed by the Technology Independent Representation of Electronic Products (TIREP) project under the auspices of the Sustainable Hardware and Affordable Readiness Practices (SHARP) Program, is called the TIREP Model Generator (TMG). The government DID, like rigorous commercial DIDs, can require standalone testbenches for each device, circuit card, assembly or specified logical and physical groupings of interest. In addition, design timing, electrical and physical data may be required in the VHDL deliverable. The TMG reads a user-generated "core" VHDL model and then prompts the user to enter design electrical, timing and physical parameters. A TMG "core" VHDL model is typically the functional VHDL entity / architecture pair (which can include timing) used for synthesis. The TMG generates a DID-compatible TIREP VHDL model. A TIREP VHDL model includes a simulatable WAVES testbench and a modified EIA-567A electronic data sheet VHDL model which documents electrical, timing and physical data and also performs timing violation checks during simulation. The user need only supply the WAVES vector file which is derived from stimulus/response vectors found in the specification or sampled from a core model simulation run. This self-documenting approach to VHDL model development yields an executable specification suitable for reprocurement, hardware design development, evaluating back-annotation synthesis timing results, design archiving and providing life-cycle design documentation. Additionally, DID-compatible VHDL deliverables (with WAVES testbenches) can be generated across physical and logical partitions by structurally connecting design entities and invoking the TMG on this new core design. The TMG provides version control and stylize utilities and supports bi-directional and tri-state I/O. The TMG virtually eliminates the learning curve and engineering expense associated with the manual generation of DID-compatible VHDL models. Whether synthesizing or specifying with VHDL, the TMG provides an automated means to generate a comprehensive VHDL deliverable. This paper reviews the capabilities, operation and applications of the TMG.
This paper presents a system for generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model, and also detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a Process Model Graph (PMG). A set of VHDL functions have been constructed to help develop VHDL models. Two algorithms are proposed to implement the test generation. P-Algorithm is used to generate tests at the process level. For each process a symbolic test set and the corresponding fixed valued test packages (FVTPs) are generated. Synthesis-related FVTP generation algorithms for the VHDL functions are derived to support the P-algorithm. E-Algorithm is employed to generate the entity level tests. The symbolic entity level tests are generated first and then the final fixed valued entity level tests are obtained by evaluating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The gate level fault coverage is obtained by using the HILO fault simulator.
Goossens defined a structural operational semantics for a subset of VHDL-87 and proved that the parallelism present in VHDL is benign. We extend this work to include shared variables in VHDL-93 that changes the underlying semantic model. In the presence of shared variables, non-deterministic execution of VHDL-93 processes destroys the unique meaning property. We identify and characterize a class of portable VHDL-93 descriptions for which unique meaning property can be salvaged.
Faced with the increasingly daunting task of verifying ASICs, designers are looking to their high-level languages for more support in the verification process. The "assert" construct in VHDL has inspired some designers to embed non-synthesizable modules in their hardware to constantly check the correctness of the VHDL design. The paper describes one designers' attempts to map the stated requirements of a design into such modules. The paper begins with an abstract treatment of the relationship between requirements, assertions, and the tests used in verification, then provides two examples in which to consider these relationships. In the first example, a PCI bus interface is peppered with ad-hoc assertions in an attempt to discover PCI bus protocol violations. In the second example, an ATM switch chip is covered completely with assertions to verify the correctness and performance as stated in the chip's requirements. The examples show the power of assertion-based verification in two different contexts - microscopic unit verification and macroscopic system verification. Based on these two examples, the paper examines some of the strengths and weaknesses of assertion-based verification and identifies some of the open issues in the field of verification.
Most modern IC designs implement complex design protocols that must be extensively tested to validate their correct operation. Exhaustive testing of all possible combinations is not feasible due to time and resource constraints. Thus, test designers must devise means to balance the amount of validation coverage and satisfy quality goals. Code coverage data can be used to determine the quality of test suite by identifying components of a design that are not exercised during simulation. This information is used to guide designers in determining the areas to focus test development effort. The use of various coverage metrics to make judgments on the quality of our test programs is discussed. Experience from several ASIC development efforts is presented.
This paper provides a user case study that shows how the complexity of designs and competitive factors in the 3D graphics market require application specific verification methodologies in order to meet time-to-market, performance and cost objectives. The article will describe the experience of designing the hardware and software for a 3D graphics application called "3D-Master" by SP3D, a joint venture with Philips. traditional and non-traditional verification methodologies will be contrasted from the standpoint of cost, performance, and results along with the investment in time and resources involved to implement application specific emulation as a key differentiating technology of the non-traditional flow. Results will be examined from the point of view of cost/benefits and ROI with a particular focus on the unique value provided by emulation vs simulation.
Modeling represents the last frontier of standards in the VHDL marketplace. VITAL and OMF model packaging are representative of the present and future of this frontier. The VITAL standard is an official IEEE standard and the ASIC and EDA vendors are beginning to adopt it. OMF model packaging is rapidly gaining momentum toward becoming the standard for distributing IP. However, standards are only useful if there is broad market acceptance of them. A brief history of both standards will be presented. The histories will be followed an exploration of the current market condition and an extrapolation of the future of these standards.
We present a template based approach for modeling monitors in VHDL with the intention to show a flexible VHDL system level modeling method. First an overview over existing approaches is given and the monitor approach is motivated. Second general software and VHDL aspects are discussed. Subsequent an application modeling of monitors in VHDL is shown. Finally we outlook towards protected Ada types, which have similar behavior as the planned VHDL shared variables.
This paper focuses on dynamic allocation techniques used when large memory addresses spaces must be modeled. The address space is often too large and sparsely utilized to be statically allocated as a simple array. Using dynamic allocation and some simple optimizations, one can model large address spaces while minimizing the time overhead of dynamic allocation and space overhead of static allocation. The optimizations covered will include hashing, linked lists, spatial locality clustering, and temporal sorting. The techniques will be demonstrated inside of a VHDL package that has been reused for many types of memory models on the Sanders RASSP program.
Hybrid modeling is a technique that can be used to integrate performance models and behavioral models within a common simulation. This approach allows behavioral components, containing mixtures of hardware and software, to be evaluated within the context of the system being developed. Hybrid interfaces are required to integrate the behavioral components with the performance models. This paper presents Honeywell's VHDL-based approach to hybrid modeling. The structure of the hybrid interface is described, and a library of hybrid interfaces, the Hybrid Model Library (HML), is presented. The Hybrid Interface Generation (HIG) toolkit, a toolkit to aid in the creation of hybrid interfaces, is also presented. We are in the process of evaluating our hybrid modeling methodology. This work is briefly discussed. Keywords: hybrid modeling; hybrid interfaces; performance evaluation; models; abstractions; multilevel modeling.
Analog and mixed-signal circuits involving only a few discrete gates are usually modeled using some version of SPICE to support simulation and behavioral analysis. With the emergence of the VHDL-AMS mixed-signal description language, there exists a need to convert many of these SPICE models into VHDL-AMS models while preserving the function and accuracy observed using SPICE. This paper describes a technique for easily converting SPICE component declarations into VHDL-AMS statements. Explicit mappings from SPICE 3 component types to both structural and behavioral VHDL-AMS forms are presented for all elementary components and sources. Device and transmission line models are not addressed. A brief description is also given of a SPICE-to-VHDL-AMS translator software program which implements the techniques.
The IEEE Waveform and Vector Exchange Specification (WAVES) standard 1029.1 [1] is a subset of VHDL specifically targeted at representing the stimulus that drives VHDL simulation models. The intent is to support users in the exchange of waveform information between different simulators and testers. By integrating a high performance, IEEE VHDL WAVES input-output capability into an accelerated VHDL mixed-level simulation environment, we can enhance WAVES ability to effectively support large, complex digital electronic system designs. The intent is to help the designer reduce design errors and shorten design schedules by using a standard stimulus format, with the advantage of mixed- and gate-level acceleration.
To reduce simulation events, a differential fault simulator simulates all faulty circuits for the same test input before applying the next test vector to the circuit. Activities occur in limited parts of a gate level circuit between application of faults for the same input vector. Adapting this fault simulation technique to the programming environment of VHDL and its use in fault simulation of sequential circuits will be presented in this paper. Modeling gate level lines and components in VHDL will be presented.
This paper presents a novel serial VHDL fault simulation technique that uses IEEE standard 1029.1- 1996, Waveform and Vector Exchange (WAVES). This fault simulation technique has several advantages over previous techniques. First, the injection of a fault into the VHDL Unit Under Test (UUT) is performed entirely in VHDL, and therefore is completely simulator independent. Second, fault injection is accomplished using the WAVES standard so the designer can use the same tools to perform fault simulations on a VHDL model that are used for VHDL model verification. This technique utilizes two WAVES processes to accomplish fault simulation. One WAVES process resides in the test bench, applies the stimuli to the UUT, and compares the actual response of the UUT, reporting any discrepancies with the expected response as the simulation progresses. A second WAVES process is added to the architecture of the VHDL UUT. This second WAVES process supplies stimuli to fault mask signals that indicate the presence or absence of a given fault on a given signal in the model. The fault mask values are interpreted by a concurrent fault injection procedure which corrupts the fault-free port and internal signals according to the fault mask value and the fault model chosen by the designer. This paper discusses fault injection procedures that have been developed to support four common fault models: (1) the stuck-at fault model, (2) the bridging fault model, (3) the delay fault model, and (4) the stuck-open fault model. Since this technique inserts fault injection capability into the architecture of the UUT, the testbench and the entity declaration for the UUT need not be modified to perform fault simulations. Finally, since the technique is based on WAVES-96, it can be applied to any level of design abstraction from gate level to performance level modeling.
In this paper we present a method for behavioral synthesis of hardware systems described in VHDL. Due to the simulation-based semantics of VHDL, most of the existing tools restrict the subset in order to facilitate the task of synthesis. The approach proposed here is based on an internal formal model in terms of Interpreted and Timed Petri Nets (ITPN). A set of equations can be extracted which allows us to perform the recognition of memorizing elements, a key step in the synthesis of behavioral VHDL, without imposing any cumbersome description style.
High-Level Design Automation (HLDA) methodologies depend, to a large extent, on the quality of implementation that HDL synthesis tools can provide. Because of the computational complexity of the synthesis problem, the quality of the input coding style is, in many instances, the largest determining factor of quality (the old adage: garbage-in, garbage-out, still holds). This paper explores the requirements and proposes an architecture for a structured approach to language-based transformations to improve design quality. There are five major steps in the process of this work: language processing, pattern matching, transformation analysis, transformation, code generation. The language processing component of this work is well documented at this point and the paper focuses on the latter four steps of the process. The pattern matching component of the process works from two standpoints: common coding practice errors and actions on the predictable portion of the synthesis heuristics. Transformation analysis is an estimation process based on the generation of a hardware-like model of the processed language. The transformation actions are algorithmic generators that operate on the native process architecture structures. The final code generation step is an attributable, parameterizable step that can be used to create additional degrees of freedom. Examples are used to describe the details of the process.
This paper discusses a hierarchical top-down parameterized VHDL design methodology [1] and its application to the design of a digital carrier recovery loop filter. The loop filter ASIC includes all critical functions such as multipliers, delay registers, accumulators, counters and adders, all of which were synthesized from a parameterized VHDL description. In the process of a top-down system design approach, design trade-offs are usually difficult due to the lack of information about the detailed hardware implementation. This paper shows through an example how hardware specifications such as gate count and critical path were obtained quickly to assist in the system level trade-offs. An analysis of area vs. speed has helped to identify the most optimal parameters which will yield the most efficient design.
VHDL and C play an important role in nowadays system design. In order to examine the applicability of these two languages for system development, we mainly focus on performance aspects but also compare the language capabilities of VHDL and C. Language related benchmarks as well as DSP applications were used for examination. We detected an about 5 times higher execution performance of C programs compared to similar VHDL models. This difference partially results from bit operations on integer and pointers to all explicitly and implicitly allocated pieces of memory, which are available in C but not in VHDL. But we also found a performance weakness of VHDL-tools primarily due to the lack of data-flow analysis based code optimization, automatic index pointer transformation, and automatic subroutine in-lining.
The development of seven ASICs required for the operation of two display-types on the F/A-18E/F was successfully completed, but the estimates for design and development based on advertised automation tools capabilities were extremely optimistic. The success of this development effort required the addition of more resources in terms of cost, time, and manpower. This paper provides lessons learned emphasizing different areas of improvement rather than accounting for every detail.
The research described in this paper was motivated by the need for fast computations of the Discrete Cosine Transform (DCT) and the Inverse Discrete Cosine Transform (IDCT) in real-time video encoding and decoding, respectively. Using VHDL for functional verification and a commercially available logic synthesis tool for synthesis verification, we have successfully developed a highly parallel architecture which is capable of computing both the DCT and IDCT. This architecture's potential for high performance is mainly due to the overlapping of communication and computation. We assumed that we could receive only one element of an 8 x n (where n is a multiple of 8) matrix per clock cycle, in row major fashion. This 8 x n block-size results from a convention in many image compression/decompression standards. Because of its pipeline structure, the architecture that we have developed can achieve a throughput of one 8 x n block being processed per 8n clock cycles. To say that an 8 x n block has been processed, is to say that the DCT or IDCT has been computed for each of the 8 x 8 sub-images within the block. This architecture includes 16 multipliers and 16 adders, which is a small hardware complexity compared to that of other DCT/IDCT architectures with comparable throughput. Furthermore, we developed a test bench, for the VHDL model, that used the TEXTIO library functions in such a way that it was not necessary for it to be recompiled when different types of test input were applied.
Electronic systems are currently developed and verified by means of CHDL descriptions. This work is supported by two main activities: simulation and synthesis, both of which are based on compiler technology. The application of this technology and its relationship with CHDL simulation is presented in this paper. Typical VHDL compilation steps are presented to introduce analysis as the last point in common between simulation and synthesis applications. With this foundation, we elaborate on the differences between the two most popular HDLs, VHDL and Verilog, in terms of compilation technology and explore the use of common data representation that can be used as a solution to CHDL interoperability problems.
This paper describes VHPI, a C programming language interface for VHDL that is under development at Cadence. The intended use of VHPI is explained and the important characteristics of the interface for accessing VHDL design information and interacting with a VHDL tool are described. Finally, the need for a standard way of including user-written C code with VHDL models in a VHDL environment is discussed.
The Advanced Intermediate Representation with Extensibility, AIRE, supports integration of advanced HDL tool components and exchange of partially compiled HDL designs. Tool components may be integrated within a single address space using AIRE's internal intermediate representation, IIR. AIRE's file intermediate representation, FIR, supports integration of tool components and HDL designs though reading and writing AIRE files. Efforts to build previous generations of HDL tools on a standard intermediate format did not converge or achieve the support of multiple vendors due to competing commercial concerns and technical problems. Earlier approaches no longer meet the requirements of today's advanced tool developers. Today, advanced HDL tools require consistent representation from analysis through runtime, true portability among tools and platforms, extensibility to support both localized and industry-wide extensions, memory / processor efficiency, intellectual property security, unrestricted access to the specification / revision process and broad HDL language scope. The Electronic Industry Association's AIRE meets these requirements for advanced HDL tools.
This paper describes a method to develop VHDL-based tools by iteratively and incrementally customizing an object-oriented VHDL internal intermediate representation. Such a method derives its need from the availability of commercial VHDL analyzers with advanced and open object-oriented interfaces which can potentially eliminate the need to develop or use proprietary analyzers and procedural interfaces, thereby resulting in considerable savings in time and money.