This paper presents a VHDL test bench for random generation of test vectors for gate level structural digital circuits. Adaptive generation of test vectors is being focused here. In this approach, one of several predetermined vector generation schemes is selected based on the anticipated fault detection rate.
This paper describes the analysis of VHDL test benches using TransEDA's code coverage tool, VHDLCover. A short description of the implementation is also given. TransEDA converted the design from VHDL to Xilinx XNF format using TransGATE, TransEDA's synthesis tool, and implemented the design using a Xilinx 4010 FPGA. The VHDL source and VHDL test benches were supplied by the client.
With the advent of HDL based VLSI design, synthesis and verification, there is an emerging need to move module and chip level testing earlier in the design cycle. The use of HDL based test benches to verify functionality could be applied to determine fault coverage for wafer sort testing. Test benches with good functional coverage should be able to provide close to, if not complete, targeted fault coverage. A VHDL simulation environment with this capability requires a VHDL fault simulation algorithm with certified gate level libraries support. The later requirement is being addressed with the VITAL effort, but efforts for the former are still in their infancy. Even if VHDL based fault simulators become available soon, it will be a few years before the simulators are able to deliver acceptable performance. To provide designers with language based testing tools today, this paper presents a VHDL based mixed level simulation environment with a fully integrated, high performance, full timing, deterministic fault simulator that supports over 120 certified ASIC libraries. This fault simulator, named Voyager FS, is integrated into the IKOS' mixed level simulation environment using a high speed simulation backplane which connects it to IKOS' VHDL simulator. A mixed level simulation architecture, with it's debugging and tracing capabilities enable designers to quickly and easily verify test patterns on module or chip level, early in the design phase. A set of benchmark results are also presented. Finally, future work to enhance performance and test capabilities is described.
The use of automatic test insertion software and WAVES (Waveform And Vector Exchange Specification) can greatly reduce the need of VHDL designers to become test experts while still implementing efficient test solutions. This paper will describe the use of a test synthesis toolset to implement the IEEE 1149.1 boundary scan and internal scan into a in-house CMOS chip design that is being designed with VHDL. The use of WAVES and self-checking testbenches to test scan operations will also be described.
Designing an efficient high speed complex state machine has always been a challenging task in the field of high speed digital logic design. In the last decade, there has been notable developments in implementing and prototyping the digital logic design in FPGA ( Field Programmable Gate Array) before making an ASIC (Application Specific Integrated Circuit). This has not only reduced the design time but also reduced the cost of the development cycle. The FPGA architecture provides various levels of flexibilities to implement high speed complex designs. Hardware Description Languages (HDLs) have emerged to aid the designers to describe a complex circuit behavior at higher abstraction level. This has led to the popularity of the VHDL (Very High speed Integrated Circuit Hardware Description Language). VHDL has become a defacto standard in describing a behavioral circuit model. The extraction and usage of all the archtectural features of FPGA using VHDL is a key issue in FPGA implementation of high speed design. In this paper, we have addressed the different issues involved in designing high speed state machines in FPGA architecture using VHDL under Synopsys Environment. We have analyzed two styles of writing VHDL code for such implementations. The authors recommend an optimal method to implement the design in Xilinx XC4000 FPGA2 family. The method, however, is also applicable to any other FPGA architecture.
VHDL is becoming the most frequently used design language for both simulation and synthesis. Some of the major factors in selecting VHDL tools are speed, efficiency, cost, and user friendliness. In our design group, multiple simulation and synthesis tools were chosen. While the main goal of VHDL is to make designs portable, today's environment does not allow this to happen. Using multiple tools in the same design environment caused several problems for the users. Considerable effort were spent in selecting the libraries to be used as well as the data types. This paper describes the reasons behind the multiple tools environment, the steps taken to provide a user friendly environment, and the experiences learned from it. Keywords: VHDL Simulators, VHDL Synthesis, Interoperability, Standards.
BLACKJACK is a VHDL-based topdown design technique for control-dominated systems. The control-dominated system is a system which has complex execution thread but seldom performs arithmetic operations. It usually consists of many parts which operate in parallel and interact with each other. The technique consists of (1) design capture with a specific, behavioral style (BLACKJACK style) VHDL and (2) a conversion program (FISGEN) that builds a finite state machine with datapath (FSMD). The resulting FSMD is described in the behavioral style VHDL that can be fed into a logic synthesis tool. One process in the FISGEN input turns into one process in the FISGEN output. In the BLACKJACK style, behavior is described with "standard" programming language construct. In addition, elapse of time is explicitly specified with VHDL statement, WAIT FOR 0 ns, that introduces one delta delay. There is no restriction concerning where it is placed. The BLACKJACK style uses a simple, uniform way of modeling interprocess signal sourced by more than one process and thus can model a design which has many parts that are active simultaneously and interact with each other. Resolved signal of bit type with an appropriate resolution function and assignment to NULL model this type of signal. Bus or register kind is used depending on whether the signal is sensed only when its driver is active or it may be sensed even when the driver is not active. The modeling is done at the level where no concept of state or state transition is introduced. The captured design is simulated with a VHDL simulator and verified. There will be no advance in time in terms of second but only in terms of delta. FISGEN traverses the flow graph of the input description, introducing state transition when no more operations are possible in the state under consideration, or when a WAIT statement is encountered. The decision about no more possible operations is based on very simple criteria that are considered adequate for the targeted application domain. Interprocess communication is converted into description from which a logic synthesizer generates register/FF with multiplexors or bus driven by 3-state buffers, depending on whether register kind or bus kind is specified. The technique was tried on several control-dominated systems, including the PCI bus controller.
The introduction of new ASIC technologies every few months begs the question of how we are to ensure the optimal mapping of algorithms to hardware. VHDL is not suitable for general prototyping at this level, but the modelling concepts in VHDL are valuable. A C++ model of VHDL can keep the relevant concepts, and provide a richer environment for dynamic prototyping. This paper describes the current state of a C++ prototyping system done at VLSI. The paper allso discusses VHDL "missing features" which make it necessary to use C++ and what these features would mean in VHDL.
One important aspect of VHDL is its ability to abstractly model hardware systems. Such models can be invaluable for hardware/software co-design and large system design. When using abstract models, VHDL users often experience great difficulty in manipulating characters and strings due to a lack of a standard set of string manipulation routines. To ease the development of behavioral models that manipulate strings, a standard string convention and the VHDL string package (VSP) is described. When employing VHDL for abstract modeling, powerful string support can simplify the code development task and the resulting model. For example, consider the case of performance models of a multiprocessor system and its interconnection network. A convenient way to encode a path through the switching fabric is an address consisting of a string of characters corresponding to the concatenation of the port names of each switch along the path. While modeling the network behavior, a number of string manipulations are required including computing the string lengths, comparing string, searching strings for patterns, and copying strings. Providing standard routines to the system modeler significantly eases the model development time and complexity, as well as increasing interoperability and reuse potential. VSP includes several routines to support character manipulation, string manipulation, and string search operations. The VSP manipulation routines assume strings are null terminated as with C [1]. A set of character and string test and manipulation routines allow character parsing for applications such as testbench support or the abstract modeling example described above. In addition, VSP provides a powerful string search capability based on regular expressions. A designer can characterize a wide range of pattern types using regular expressions and quickly search strings for pattern matches. The Std_DevelopersKit provides similar functionality for string manipulation and also supports string conversion and file I/O, but does not include the string search and pattern match capabilities of VSP [2]. The character manipulation routines include:
During Autumn 1994, engineers at VEDA Design Automation created Level 1 VITAL compliant versions of LSI Logic's LCA300k and LCB300k libraries, VLSI Technology's VSC670 library and Xilinx's 2000, 3000 and 4000 libraries. This paper aims to communicate some of the 'do's and don'ts' of VITAL modeling we have encountered. We begin by discussing what makes a model Level 1 compliant, focusing on two tricky topics, writing state-tables and resolving ambiguities in version 2.2b of the standard. The discussion of state tables leads onto one of the more controversial aspects of VITAL, whether or not to allow multiple processes in models. We then consider how to write memory and PCB models, which are currently not covered by the VITAL standard. Finally we look at the software VEDA used to automate the task of model generation.
This paper presents a method for efficiently modeling the performance and behavior of a multi-processor Digital Signal Processor (DSP) system in VHDL. The need for top-down simulation based design techniques, as developed under the Rapid prototyping of Application Specific Signal Processors (RASSP) program, calls for VHDL models that are more abstract than usual. In the described method, a highly abstract performance model is extended to form a comprehensive virtual prototype of a full DSP system that is timing- and data-faithful. Full-system models provide early design verification by simulating application software, as partitioned, mapped, and executed on a hardware architecture. The VHDL modeling techniques enable integrated hardware and software co-design development. An architecture independent software description together with selection of an appropriate modeling abstraction level permit the rapid exploration of many hardware/software candidates without sacrificing simulation accuracy or efficiency. The results of applying this technique in the design of a real-time synthetic aperture radar processor are reported.
Robust modeling is a critical ingredient for a successful multiprocessor system design methodology. This paper will present details of VHDL-based modeling developed by the Honeywell Technology Center. This modeling approach emphasizes multiprocessing and distributed communications with accurate and flexible workload representations. The resulting performance analysis can be applied to multiple levels of abstraction for both software and hardware. In the process of designing and implementing our performance models, we have stretched VHDL from its traditional hardware origins to a great extent, discovering the advantages and the limitations to the language. This paper highlights both the advantages of VHDL for complex system modeling, as well as several maneuvers required to work around significant language limitations.
This paper addresses the modeling of hardware systems at high levels of abstraction. To support VHDL-based abstract specifications, a new modeling language is introduced and demonstrated that supports defining the abstraction linking specification models to designs. This language, called VIL (for VHDL Interface Language), provides a capability missing from existing hardware simulation environments. The manner in which this language supports greater verification rigor and automation is also described.
The increasing complexity, time to market pressures, and life-cycle-costs of digital signal processing (DSP) systems have motivated development of new design and prototyping methods. In particular, hierarchical VHDL model-based design techniques were developed and are being demonstrated as part of the ARPA/Tri-Services sponsored Rapid-prototyping of Application Specific Signal Processors (RASSP) program. Meeting the rapid prototyping challenges requires unambiguous transfer of design information and communication about modeling modes between developers. To address the need for conventions in modeling and terminology, the participating organizations of the RASSP program formed the RASSP Terminology Working Group (RTWG). Based upon examination and comparison of previously published modeling taxonomies, the working group is evolving a multi-axis taxonomy designed to describe the information content of VHDL model types and abstraction levels and to facilitate selection and construction of interoperable models. The RTWG used the taxonomy to concisely refine the definitions of modeling terms that are especially important in RASSP.
The paper addresses parallel VHDL simulation, especially for performance and behavioral simulation. We are implementing Time-Warp protocol on massively parallel processor machines so that a speed-up of up to a hundred times can be achieved compared to sequential simulation. The target machine is SP2 with 480 nodes, but MPI, a standard machine independent communication library, is used to make the parallel program portable and scalable. We have selected a subset of VHDL constructs to describe the performance and behavioral models. A translator is being developed which generates a C-subroutine and a table for each VHDL process. The table contains delay of each signal assignment, sensitivity list, among others. The communication scheme on SP2 using MPI is discussed. We also present an efficient scheme of computing global virtual time (GVT) which is necessary for fossil collection to free up memory space in the Time-Warp mechanism.
Parallel VHDL simulation has emerged from solely being a subject of academic interest into an area of practical utility. This paper presents a taxonomy of parallel VHDL simulation techniques as they are actually manifest in a variety of parallel VHDL simulators. The IEEE DASC group on parallel VHDL simulation is using an evolution of this taxonomy as a key to simulator-specific recommended VHDL coding practices for efficient, high-performance parallel VHDL simulation.
The time warp synchronization mechanism has the potential to speed up VHDL simulations on parallel platforms. However, practical implementations of time warp have been hindered by several drawbacks such as large memory usage, excessive rollbacks (instability), and wasted lookahead computation. These problems have been addressed by a variety of optimizations and variations to the original time warp mechanism. While many of the optimizations show good isolated performance, they remain unable to satisfy the objectives of realizing good performance against a broad range of simulation problems. Fortunately, many of the problems are addressable by the addition of dynamic parameter adjustment. A Parameterized Time Warp mechanism is presented that provides a simple integrated solution to the problems associated with the original Time Warp mechanism. The mechanism is based on parameters of useful work that represents the amount of productive work done by each LP. We use these measures to update the following parameters in a time warp simulator: (i) checkpoint interval , (ii) cancelation strategies, and (iii) bounding windows. In addition, viewed as a controllable system, new, less intrusive GVT algorithms for time warp have been developed.
This paper describes a standards based approach to providing the infrastructure needed to support systems verification. The issues of the model availability, protection of intellectual property, and the semantics of mixed language verification systems are addressed.
As the majority of VLSI designs migrate to the submicron and deep submicron processes, design complexities continue to increase at a rapid pace. There is no corresponding increase in the design cycle, and the designers are challenged to increase their productivity. HDL (Hardware Description Language) based top-down design methodology can be used effectively to help cut the design cycle. The choice of the HDL, VHDL or Verilog, has a different impact on the design methodology. While they have overlapping scopes, they do have complementing strengths. Today's designers can leverage these complementing characteristics and successfully design next generation products. This paper will enumerate our experiences in the application of both VHDL and Verilog for a successful design methodology.
VHDL and Verilog have gained tremendous popularity in today's CAD world that a lot of CAE vendors are coming up with methodologies and tools to operate both of them in a single environment, commonly referred to as cosimulatlon. Some of the advantages of this cosimulation are to protect ones investment in the existing models, to provide mixed-language simulation and allow interoperabilty between simulators. This paper describes cosimulation concepts to exploit the existing Verilog/VHDL descriptions to operate in a coupled manner. Cosimulation can be effectively used to link some of the modeling abstractions described in VHDL and Verilog. The intricacies, usefulness and limitations are described.
This paper begins by analyzing current market developments to discover why fault simulation is enjoying a renaissance. Having established why fault simulation software is still needed, it examines why traditional fault simulation algorithms are not ideal for VITAL netlists, and outlines new algorithms, based on set theory, which give accelerated performance for VITAL based fault simulation. Finally, the paper suggests that extensions be considered to the VITAL standard so that faults may be modeled such as stuck-open, bridging, and delay faults for CMOS circuits.
This paper presents some of the Inter-standard related issues impeding VITAL standardization efforts for fast and accurate simulations and ease of modeling. The issues described in this paper are as follows: 1. Skew checks for Differential and Phase detector cells 2. PATHPULSE implementation issue related to VHDL'87/'93 3. Annotation definition when a "generate" statement is used in VHDL 4. Labels for big string names as part of conditional path annotation 5. Logic value system for representing strengths All the issues are covered with some realistic examples and the current work arounds of implementation. The paper finally gives the extensions and features required to SDF constructs and VHDL language to address these issues in an elegant way.
This paper describes a new modelling concept for the timing simulation of digital electronic systems with special respect to the influence of interconnections. A new signal representation allows the modelling of waveform dependencies, accurate models for interconnections will catch the increasing influence of that passive part on the overall performance of electronic systems, using information extracted from layout data. The models are implemented in VHDL, some modules in the programming language C, which can be linked to a conventional VHDL-simulator. VHDL-netlists, e.g. generated by synthesis tools, are automatically modified to use the new signal representation and models.
This paper presents a design system that significantly speeds up development of VHDL behavioral models with back annotated timing. The behavioral model is developed using the CAD tool called Modeler's Assistant by inputting the model in the form of a Process Model Graph. The back annotation tool Backann uses the VHDL description from the Modeler's Assistant, the Compass-VTIP CAD tool and the Synopsys Design Compiler to calculate the timing delays and to back annotate the delays into the behavioral model. The Compass-VTIP tool is used to extract the details from the VHDL model and store it in the form of data structures. These details are used for computing the paths traversed by the signals associated with the generics. The behavioral model is synthesized into a gate level design and the end to end delays in the model are obtained using Synopsys Design Compiler. An algorithm has been developed which, given the end to end delays and the different paths traversed by the signals, finds realistic and accurate delays for processes along the path. Thus a system is available to designers which builds behavioral models with accurate timing information.
In this work, VASP - Power Simulator is presented which estimates the total power consumed by a design represented at RT Level (Architectural) in VHDL. Power simulation consists of the following tasks: (a) characterization of the module library, (b) simulation of the VHDL structural description. The module library consists of register level modules such as adders, registers, multiplexors. In the VHDL Libary, for each module two architectures exists namely, one-bit and n-bit. The one-bit architecture has capacitance measuring code embedded in it. The n-bit architecture is an instantiation of 1-bit architecture using generate statement. Thus the module library characterization is very fast as it is done only for 1-bit architecture. For a given VHDL structural description, it is simulated using a VHDL simulator and a power profile is obtained.
Object-Oriented System Engineering (OOSE) is a mature, proven system development methodology [1] that, when applied to VHDL-based hardware development programs, provides extraordinary improvements in quality and efficiency. The process offers intuitive, highly efficient graphical representations of complete systems at various levels of definition to illuminate otherwise opaque technical issues. As with VHDL itself, OOSE constructs can be applied with equal ease at multiple levels of abstraction to document requirements, design and implementation. OOSE is a malleable framework designed to be tailored to meet a variety of development scenarios guiding the application of resources, methodologies and tools. It is an ideal platform for managing quality and maintaining development efficiency across many product generations. This paper presents an introduction to OOSE as applied to challenges familiar to integrated circuit developers.
Advancements in silicon technology are increasing the number of transistors per die while synthesis capabilities are increasing the number of gates that can be designed. These two industry trends are putting heavy pressure on design verification because "gate" creation is rapidly outpacing "gate" verification. With the advent of Cycle-based logic simulation, improvements have been achieved that provide orders of magnitude improvement in software VHDL gate simulation throughput and memory utilization without the high cost of accelerators and emulators.
A new process for automating the creation of Full-Behavioral (FBM) and Instruction Set Architecture (ISA) models in VHDL for complex processors and components is described, with results from the automation of a PowerPC 601 described in some detail. A number of advantages to this approach are described together with its impact on the hardware/software codesign and system prototyping processes.
As the density and complexity of FPGA-based designs has increased to 10,000 gates and beyond, the use of high-level design languages (VHDLs) is rapidly supplanting schematic entry as the preferred design entry format. However, to obtain the best results, the hierarchical design techniques already familiar to schematic users can be even more critical in an VHDL-based design. Furthermore, the choice of partition size can be critical to meeting capacity and performance goals, as demonstrated by the implementation of a 15,000 gate design.
Fault injection provides a method of assessing the dependability of a system under test. Traditionally fault injection is employed near the end of the design process after hardware and software prototypes have been developed. In order to eliminate costly re-designs near the end of the design process, a methodology for performing fault injection throughout the design process is described in this paper. The Walker-Thomas model of design is used to abstract system design into multiple levels. The fault injection methodology is applied to the design of a watchdog monitor card in a distributed computer system. Simulation results illustrate the fault injection methodology at multiple levels.
The current problems in adopting VHDL as a Hardware Description Language for a microcontroller design project are the design methodology and generating VHDL code which will map to appropriate hardware. This paper describes the design and validation approach used to develop a general purpose microcontroller. In addition, it describes VHDL code writing styles, which will map to desirable hardware. Also, it will discuss various optimal synthesis strategies.
With the advent of increasing system complexity and the need to meet shrinking schedule and cost targets, new methodologies for improved first time success to market need to be explored and developed. VHDL over the past several years has focused on the structural and register transfer level (RTL) of coding. This yields a low gates per line of code metric. If the gates per line of VHDL are to increase then methodologies based on using higher levels of abstraction will need to become more usable and widespread. Over the past four years Raytheon has successfully used VHDL to design ASICs, modules, subsystems, and systems. During that time several different methodologies were explored. This paper will examine those methodologies and historically show a progression from the early benefits of using various RTL methods to the latest design flow using behavioral synthesis. This latest methodology allows true system design with significant reduction in the number of lines of code, manpower, and schedule. In comparison large system designs using RTL VHDL require many more lines of code, thus increasing model complexity, the risk of error and causing longer compile and simulation times. There are obvious tradeoffs and limitations when higher levels of abstraction are used and some of these details will be presented.
This paper presents two new tools integrated in the Syntax Driven Editor for VHDL: SDEV[1]. The first tool allows the user to build his own VHDL subset. The second is a tool which allows to verify if a VHDL source belongs to a given VHDL subset. This paper is illustrated through the example of the subset used for the SYNOPSYS synthesis tool.
The different issues to consider when designing and modeling Finite State Machines (FSMs) in VHDL for use with RTL level synthesis are shown. The issues covered are: coding style, resets and fail safe behavior state encoding, Mealy or Moore type outputs, additional sequential next state or output logic, and interactive FSMs. VHDL models are included.
Most of the commercial VHDL simulators provide some form of interface to C functions and procedures in a VHDL simulation environment. But, there are no methods described to interface VHDL models in an executable C specifications environment. This paper describes an interface that provides transparent simulation of VHDL models like C functions from an executable C specifications environment. The new interface has been successfully used to simulate VHDL models with the executable C specifications of a large design.
Increasing complexity, tight development schedules, and small budgets characterize the present design process of electronic systems. Therefore, the reuse of design know-how and existing design data is of great importance. VYPER! supports the reuse of any arbitrary collection of VHDL source code by an automatically generated documentation environment. Hypertext links and abstract graphical design representations ease the understanding problem during the reuse of unknown designs.
The need for flexible, mixed-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever decreasing product cycle times. The simulation development team at IBM-Rochester was challenged to create a portable mixed-level simulation environment to assure correct functionality of the I/O bus and memory subsystems for the next generation of PowerPC systems. Since this new environment was to be used to verify a wide range of memory and I/O bus architectures, it had to be both robust and adaptable. The chip development teams also required that the testcase results be self-verifying requiring little or no specific "expected value" details from the user. To further enhance the effectiveness of each simulation environment, both random test conditions and bad-machine-path functions were added to the user's testcase command language. The resulting simulation environment is based on a network model and makes heavy use of mixed-level simulation techniques. The network manager as well as the high-level I/O bus and memory models are written in sequential VHDL.
This paper presents the results of a study to examine the effects of various VHDL model characteristics on simulation execution times. Four different modeling characteristics of complex VHDL models were examined: the size of signals, the use of file input and output (I/O) operations, the use of bus resolution functions, and the overall size and complexity of VHDL models. To develop models and tests for these characteristics, the University of Virginia's Advanced Design Environment Prototyping Tool (ADEPT) was used. This performance modeling environment provided an easy framework to develop tests for the four characteristics to be examined. After developing the different tests to examine these characteristics, multiple runs were conducted to minimize random variations due to processor loading. The results of these tests are presented here along with detailed explanations of how each test was developed and conducted. From the results presented here future VHDL model builders will be able to develop more efficient models by knowing the effects different model characteristics will have on their simulation execution times.