This paper presents a design methodology and interactive test bench techniques for VHDL environments focused on the reduction in the gate level simulation to behavioral description verification cycle time. The methodology leads to the creation of a VHDL test bench simulation environment that simultaneously stimulates both the behavioral VHDL system description and the gate level model so that simulation run-time verification of the outputs can be made. The interactive test bench techniques presented allow the designers at both the system and the component level to streamline test benches and to create a more efficient debugging and testing environment. A detailed example of the methodology and the test bench techniques is presented for the implementation of an IEEE 1149.1 JTAG TAP controller.
This paper takes a look at current design and verification trends and why acceleration of VHDL execution is desirable. It compares various VHDL simulation techniques and presents a new VHDL simulation environment based on a custom hardware and software. This strategy is targeted at improving VHDL performance and has proven capable of significantly increasing VHDL execution speeds, particularly for behavioral and RTL level models.
This paper presents a package for developing testbenches that are easy to write, are easy to maintain and automatically check the results against the expectations. These testbenches not only allow for the separation of the test patterns and the automatic checking from the VHDL but also simplify the process of generating the VHDL code so that a fairly complex testbench can be written in a matter of minutes. The package being presented incorporates procedures and functions that will read symbolic commands from a pattern file and parse them into a set of vectors and checks for the design being tested. The testbenches that can be created with the package are suitable for testing any design that can be fully verified through its ports. This paper goes through the development of all of the procedures and functions in the package and also presents an example design and the VHDL code and stimulus file that could be used to fully verify the design.
This paper shows how to set up release management using basic UNIX utilities, such as RCS and make. The scheme that is presented prevents new releases from affecting simulations that are already in progress and allows users to choose which release they would like to use, even allowing them to substitute experimental code in the place of a released module. The paper walks the reader through an example project, demonstrating how to set up the directory structure and develop the appropriate scripts and makefiles that will automate the environment.
This paper describes the author's experience using VHDL based logic synthesis with an object oriented methodology in the development of ASICs. Application of this methodology results in designs that are produced more quickly, designs that are capable of being reused, and designs that are more likely to work the first time.
This paper reviews the different implementation architectures of several digital filters, using synthesizable VHDL. The key issue on developing functions with VHDL descriptions is that VHDL allows usage of a number of parameters while developing DSP functions, but it also requires an optimized VHDL coding style for a specific synthesis tool. A recently created VHDL macro function library provides different kinds of realizable filter architectures for a variety of DSP applications. The library functions are parameterizable and generic. The library development started from the industry requirements to increase the design efficiency of ASICs, and to enable a rapid evaluation of various implementation architectures.
This paper highlights the various aspects of ASIC gate level modeling and how VITAL addresses the ASIC sign-off requirements. While designs are becoming larger, the models are also becoming complex with the need to model accurately the various technological effects in the submicron era. While performance and accuracy are contradictory requirements in an ASIC library, the modelers maintain a compromise between the two while developing the library. Some of the complex behavior in ASIC cells and the modeling practise that can be used in VHDL using VITAL specification is discussed. Also some of the requirements for implementation in packages are listed.
This paper examines the Object-Oriented Features that are present in VHDL, such as, abstraction, encapsulation, modularity, polymorphism etc., also examined are the features that can be incorporated in VHDL, such as inheritance, that will enhance the development, maintenance and usability of VHDL component models. Examples have been provided to illustrate the object oriented features available in VHDL. Examples of Object-Oriented extensions to VHDL, based on the preliminary work done in this area have been included. The goal of this paper is to leverage existent ideas towards standardized or customized extensions to VHDL, and to educate designers in being systematic about model development. A view on the current proposals related to Object-Oriented extensions to VHDL, coming from the shared variable group and the initial findings of the working group on Object Oriented extensions to VHDL is also included. 1. Object-oriented Modeling and Design - Rumbaugh, Blaha et al., Prentice Hall. 2. Object-oriented Software Construction - Bertrand Meyer, Prentice Hall. 3. OO-VHDL: Object-Oriented Extensions for VHDL, Presentation by Vista Technologies, DAC 1994, OO VHDL Study Group.
This paper discusses minmax simulation for logical circuits and suggests a VHDL implementation methodology for this simulation. The document starts with definition of minmax and how it relates to the timing analysis of digital circuits. This is followed by presentation of an approach for minmax simulation. We will then show the VHDL implementation of this approach. We will also suggest ways in which VHDL can be improved to help the implementation of the minmax models more efficient to simulate.
A chipset has been developed for Synchronous Optical Network [SONET] applications. The chipset consists of a four channel T1 framer, a seven channel T1/SONET mapper and a SONET overhead termination device. One of the key features of the VHDL based development methodology used is the behavioral VHDL testbench. The testbench enabled the team to check and re-check the design for compliance to telecommunications standards throughout the development cycle. The testbench cut design time by eliminating the need for vector creation. Furthermore, through the use of a mixed-level gate/VHDL simulation environment, regression testing of the chips at the behavioral, RTL and gate-level phases was made possible. This paper will describe the general development methodology used on the chipset, and specific aspects of the testbenches used.
In this paper we will present techniques for simulation, test and documentation of digital circuits. The techniques present VHDL coding styles for modeling characteristics of digital components for the purpose of simulation, test, verification and documentation. The paper consists of five sub-sections, each describing an application and a VHDL coding style and the modeling technique that suits the application. The techniques presented here are for 1) BDD representation and lookup, 2) Reducing simulation time of flip-flops by use of alternative clocking schemes, 3) Detail logic simulation by considering rate of change of signals and a threshold value, 4) Developing a generic unconstrained state machine model, and 5) Modeling for critical path tracing for test and fault simulation applications.
Since data path and controller are often written as separate subsystems a technique is needed that makes the VHDL code readable (self-documented), easy to change, and less error prone. At first glance there seems to be no problem at all. But the real problem occurs when describing real systems, like CISC processors, with many control signals from controller to data path. Furthermore this number of control signals often changes regularly during the design process. This paper describes a technique that will be appropriate if the number of control lines changes during the design process. Furthermore the requirements mentioned earlier are preserved.
Building system simulations in VHDL can sometimes be an intensive and complicated task. Usually a major part of that task involves modeling bidirectional networks such as backplanes, motherboards and even connections between ASIC's on a printed circuit card. Many of these networks involve a delay of some kind. This paper presents a concept for a bidirectional wire model which can contain a delay specification.
Building models and testbenches in VHDL can be a harrowing as well as exciting and creative task. This paper presents two common, VHDL structures which are well known and easily understood : multiplexers and data queues. It is hoped that the identification of some of the "gotchas" in these structures will help preclude inclusion of bad language choices into otherwise good model designs.
The structure of a file-driven, programmable VHDL bus functional model (BFM) and its application for design verification within a simulation test bench is presented. The model emulates the behavior of a microprocessor bus interface to memory and I/O. An example implementation is shown for the Honeywell RH32 RISC microprocessor, although the generalized techniques can be applied to any microprocessor bus. The structure of the BFM is described in detail. A command language for the BFM is defined, including bus commands. The model provides the ability to perform board-level simulations with a high level of fidelity, without requiring a detailed model of the microprocessor being emulated. Additionally since the model is file driven, it supports stimulus file revisions and multiple versions without re-compilation of the VHDL testbench.
The VAST project implements a parallel, optimistically synchronized, VHDL simulator on a network of Symmetric MultiProcessor (SMP) workstations. The VAST simulator targets the parallel execution of behavioral VHDL models across a network of heterogeneous SUN (Sparc) workstations. The workstations are heterogeneous in that they can be single processor, multiprocessor or configured with various sized local memory. Within each SUN workstation, the processes execute as lightweight threads. A parameterized communication subsystem was locally developed for the VAST that transparently implements message passing in shared memory or through SCRAMNet or Ethernet as capacity permits. Performance analysis of the VAST simulator execution speed and space including scaling as a function of available resource (e.g., CPU's) is also being conducted.
VHDL Initiative Towards ASIC Libraries (VITAL) Model Development Specification (MDS) v2.2b has passed the ballot and has been turned over to IEEE for standardization. In the meantime, numerous technical issues surrounding VITAL MDS and packages start to be uncovered. An automatic model generator which creates accurate VITAL models comes in handy. ASIC vendors can generate VITAL compliant models with little effort. Generated VITAL models can be simulated and the results can be verified against expected simulation results. This will help in rapid identification of potential enhancements in current VITAL MDS and packages to achieve sign-off quality. Generated VITAL models can also help standardization process as "testcases" for the standard can be easily created. The generated VITAL libraries have very low maintenance cost. They can be re-generated as soon as the model generator is updated for VITAL issue resolution and updates to the MDS. This paper presents an automatic VITAL model generator. It creates pin-to-pin delay style level-1 compliant models for ASIC libraries. This paper describes in detail the different strategies applied in the model generator for modeling library cells. The correlation between technology library modeling styles and the generated models is also discussed. This model generator provides a good tool for supporting industry-standard VHDL models at very low cost.
Extensive use of VHDL at board level has been prevented by the lack of VHDL models of commercial components, and by the inconsistency of the existing ones. It is then just time to standardise modelling practices to assure that models to come will be compatible for simulation. This paper presents some thoughts about the need of an end-user in terms of models and studies the current proposals EIA 567-A and VITAL against these needs.
Surprisingly, one of the things that a system simulation engineer is least likely to be doing is simulating your system. This is partly because modern system simulation environments must constantly be evolved to include the fastest, latest tools in their attempt to verify as much of complex systems as possible prior to fabrication. This is especially true of systems containing ASICs. Frequently, environments must also be customized for each system by the addition of special data generation and checking algorithms. System simulation methodologies that use VHDL as a backbone can leverage it's standard nature when they are evolved to include new tools and features. The extensive use of VHDL also simplifies the verification of the many levels of a system including mother boards, daughter cards, boot code, and interfaces, as well as ASICs, FPGAs, and their interfaces to each other and the rest of the system. This paper describes some of the infrastructure the system simulation engineer is responsible for building, maintaining, and evolving, some of the techniques we used, and some of the places we expect to go in the future.
This paper reports on efforts underway in the Rapid prototyping for Application Specific Signal Processors (RASSP) program to establish seamless design methods based upon VHDL. The efforts place new emphasis on VHDL usage beyond the traditional detailed hardware level. VHDL will be relied upon to convey design information throughout the design process - from the initial multiprocessor system concept, down to synthesizable chip descriptions. Methods based upon executable specifications in VHDL are being established to enhance of design automation tool suites that accelerate the prototyping process through tight integration and seamless operation.
A typical electronic circuit or system development cycle begins with designers who are tasked with developing, for example, their company's next generation processor. They will try to tweak as much performance as possible out of their designs and generally, when they are satisfied with the design, they will "throw it over the wall" to the test engineers, who then have to generate the test programs and vector sets. There is a need for a methodology that employs industry standards, such as the VHSIC Hardware Description Language (VHDL)[1] and the Waveform and Vector Exchange Specification (WAVES)[2], which encourages design and test engineers to work together throughout the design/test cycle. This paper describes a technology project in which the IEEE standards, VHDL and WAVES, are being utilized within a top-down design methodology, and throughout the design through test cycle of a modest size VLSI chip.
The popularity of "cell based design" is increasing due to shortened design cycles and ease of use. Chip design tools are proliferating as small EDA companies innovate. In the past, the combination of these two trends has led to an explosion of proprietary, non-standard macrocell libraries. This paper discusses automatic generation of VITAL compliant ASIC macrocell libraries from an existing intermediate format, such as Verilog, or CDF. The VITAL initiative is an attempt to "accelerate the development of sign-off quality ASIC macrocell simulation libraries written in VHDL by leveraging existing methodologies of model development". This paper discusses automatic generation of macrocell libraries for logic simulators, synthesis tools and timing analyzers. The concepts discussed in this paper are implemented with a software tool called the Advanced Library Tool (ALT). Because the conceptual model built into ALT matches published VITAL modeling standards so closely, VITAL compliant ASIC macrocell libraries can be generated relatively painlessly.
The advances in object-oriented techniques in recent years have had a major impact on software development methodologies. It has become clear that these techniques offer significant advantages over more traditional "structured development" approaches throughout the software life cycle. Due largely to these insights, researchers have begun to explore the possible role of object-oriented technology in the development of hardware and mixed hardware/software systems. Hardware description languages, and in particular VHDL, often play a central role in the development of these systems. As such, a specific topic of interest is how VHDL would benefit from object-oriented technology and what corresponding benefits would accrue in the hardware development process. In this paper we explore the idea of "object-oriented extensions" to VHDL, survey the work that has been done in this area, compare and contrast approaches, and make recommendations for further work.
A technique has been developed that allows for the injection of faults into a behavioral-level model of a component. The corruption of a VHDL signal (that is, the fault injection) is accomplished using a bus resolution function (BRF) and an additional process statement (the fault injection process). This process corrupts the VHDL signal based on information read from a text file. The file contains the time to start the fault injection, the time to end the fault injection, which signal to corrupt, and how to corrupt the signal (that is, which bits to stick at a 1, which bits to stick at a 0, and which bits are not affected). The process statement communicates this information to the BRF via additional fields defined for the signal. This technique has several advantages over other techniques. First, the technique is simulator independent since the fault injection is accomplished with standard VHDL features. Second, the technique uses standard VHDL types to perform the fault injection. Third, the fault injection experiment information is communicated to the simulation via text file I/O. Finally, this technique can be applied to existing models with minimal changes to the existing models.
This paper describes SpeedWave/MT, a parallel VHDL simulator which uses multithreading to achieve simulation speedup on Symmetric Multi-Processing (SMP) machines. We take advantage of the inherent parallelism in VHDL, and also recent technology advances in both hardware and software for SMP machines to speedup VHDL simulation. Our approach parallelizes the execution of signal updates and VHDL processes in every simulation delta cycle. Multiple POSIX-style threads are created, up to the number of physical processors, to execute the computation tasks in parallel. Threads communicate with each other through shared memory and use spin lock for synchronization. Simulation speedup is expected for VHDL models with high activity at any simulation instant and high granularity of each computation task. Our simulation experiments show up to four times speedup on an 8-processor SMP machine with real world circuits.
The ultimate aim of the VITAL standard is to encourage the adoption of VHDL by accelerating the creation of ASIC libraries suitable for sign-off simulation. This paper looks at the practical aspects of using VITAL for sign-off simulation, writing the models themselves and developing a supportive EDA design environment for maximum productivity.
As part of the Rapid Prototyping of Application-Specific Signal Processors (RASSP) program, Vista, along with Martin Marietta Labs (Moorestown, NJ), has identified new object-oriented (O-O) constructs which can be implemented on top of VHDL with the aid of a language pre-processor. These object-oriented VHDL enhancements will be incorporated into the RASSP methodology's goals of using object-oriented analysis/design, rapid prototyping, and performance modeling to achieve major productivity gains. The preprocessor approach allows models defined in the new O-O extension language, OO-VHDL, to be used in conjunction with existing VHDL simulators and other tools.
Downsizing in the Department of Defense (DoD) and reductions in DoD funding place special emphasis on extending the life cycles of existing equipment and instituting "on demand" rapid manufacturing practices. These objectives necessitate the development of new engineering methods which address obsolescence issues and tightly couple the design and manufacturing interface. To this end, the Standard Hardware Acquisition and Reliability Program (SHARP) office sponsored the Technology Independent Representation of Electronic Products (TIREP) project to investigate VHDL circuit card assembly (CCA) modeling approaches which serve to drive a manufacturing interface. Compliance with the government VHDL Data Item Description (DID, DI-EGDS-880811) and applicability to high level design techniques were the primary criteria imposed upon the TIREP VHDL models. The DID is one provision which may be appended to government contracts to stipulate the format and content of VHDL models of delivered systems, subsystems, and components such as gate arrays and application specific integrated circuits (ASICs). The TIREP CCA VHDL models employ familiar industry standards such as the Multi-value Logic System for VHDL Model Interoperability (IEEE-STD-1164), the Waveform and Vector Exchange Specification (WAVES, IEEE-STD-1029.1) and the Commercial Component Model Specification (EIA 567/A). This paper presents the results of the TIREP VHDL modeling effort and offers guidelines for the development of component and CCA VHDL models which are compliant with the government VHDL DID. Modeling issues not explicitly addressed by either the DID or EIA 567/A are presented and a modified EIA 567 approach which minimizes code redundancy with hierarchical CCA VHDL models is also discussed. The impact of the more recent EIA 567A specification on DID-compliant VHDL modeling is reviewed. The paper also presents one VHDL coding approach to capturing Printed Circuit Board (PCB) form factors and layout directives required by a rapid acquisition manufacturing interface.
Techniques to capture complete systems are currently being investigated. The concept of a single hardware description language for all aspects of hardware design is euphoric. This paper addresses a plausible solution for complete system design. Use of the MIMIC and VHSIC Hardware Description Languages to represent and describe a typical system problem is presented. Particularly, the paper focuses on the use and interaction of the MHDL and VHDL interface.
ASIC designs developed in VHDL need to be simulated at netlist level for functional and timing verification prior to sign off. Most ASIC vendors only provide macro cell libraries in Verilog-HDL. To make use of these libraries the VHDL test setup must be ported to Verilog environment. This problem can be solved by simulating the Verilog netlist in VHDL simulation environment. This paper discusses the use of VHDL-Verilog co-simulation environment.
During the balloting of VHDL 1076-1993, one new language feature accounted for a significant portion of ballot comments and negative votes. That feature was shared variables. As a result of general dissatisfaction with the 1076-1992/A [VHDL92A] language implementation and the inability of the language design team to agree on a resolution, 1076-1992/B [VHDL92B] removed all mutual exclusion semantics, thereby creating something more appropriately termed global variables. Once again, shared variables dominated the issues raised in the balloting of 1076-1992/B. However, the VHDL Analysis and Standardization Group (VASG) anticipated the dissatisfaction and promised the balloters that should the B draft of the language pass ballot, a working group would be formed and chartered with the sole task of resolving the shared variable implementation in VHDL. The Shared Variables Working Group was formed in February 1992. This paper will address the working group's progress to date, provide an historical context, review requirements for shared variables and preview the proposed shared variable language revision.
This paper employs the challenge of designing multiple generations of a computer system to motivate use of data type encapsulation, multiple-inheritance and late-binding properties of a hardware description language (HDL). Having suggested use for these three "object-oriented" language capabilities, the paper proposes minimal extensions to VHDL which provide data type encapsulation, multiple-inheritance and late-binding while retaining upward compatibility with VHDL.
A procedure is described for parametrically characterizing the run-time performance of VHDL simulation tools and accelerators. An initial suite of three parameterizable models is proposed as a strawman toward the development of a standard benchmarking suite. Similar efforts have been proposed, and are in-progress, for developing a validation suite for VHDL simulators. This effort attempts to measure performance only: not compliance with the 1076 LRM. The relative performance of the various VHDL simulators is not well understood. Vendors and users currently compare simulators based on individual benchmarks. However, since simulator performance depends greatly upon the nature of the models that are simulated, potential users cannot reliably predict the turn-around times they will experience in exercising their models. The successful scheduling of large design projects, such as for RASSP [1], requires accurate estimates of simulation turn-around time to determine the level of modeling that can reasonably be accomplished. Since a simulation run could consume from minutes up to weeks, accurate prediction of the completion time prior to execution becomes advantageous. A suite of three parameterizable models is used to explore the performance space. Measurements of analysis and simulation memory-consumption and run-time are collected from the test case models over various conditions. The test cases contain eleven attributes which provide for linear and independent variation of the modeling conditions. Parametric coefficients are then estimated through the use of a curve fitting technique that fits a curve to the measured observations. Inspection of a simulator's resultant performance coefficients provides a concise understanding of a simulator's comparative strengths and weaknesses. An example of the application of the parametric expression is demonstrated for estimating the run-time of an arbitrary design. The accuracy of the resultant prediction should be tested by applying it to cases that were not used in collecting the curve-fitting data. The technique can be applied to characterize and compare VHDL simulators. It should serve as an aid to improving the performance of existing tools over time and to understanding the impact of modeling abstraction levels, and as a guide to developing efficient modeling styles.
This paper develops a set of requirements for portable and secure dissemination of models, then advocates a technology meeting these requirements. This technology provides for source code integrity, portability among simulators, portability among hardware platforms, tool-specific optimization and vendor independence.
This paper is based on work done at VLSI Technology on a number of ASIC designs. It addresses several important issues from the ASIC supplier point of view: how to capture the customer's design [intent] in a specification; how to encapsulate the information; how to communicate design issues. VHDL is used to create a working specification, which is then used by an engineering group. The specification [testbench and models] is expanded and refined through the process. The focus is on creating and maintaining models at different refinement levels. VHDL is used to tie all the tools and models together. The resulting flow is a step by step design process covering the customer and foundry activities. The complexity of design is simplified by model orientation. The focus is always on producing the next model.