The design and architecture of an Accelerator for VHDL Simulation (AVS) is presented which shows promise of gaining up to 1000-fold increase simulating a mix of VHDL descriptions over common second-generation industrial VHDL simulators. By exploiting advanced microelectronics technology, performance-tuned architecture configurations, and parallelism, a 256-node parallel computer should be capable of simulating structural, mixed-level, and behavioral VHDL descriptions consisting of as many as 1,000,000 lines of code, 100,000 processes, and 100,000 signals. This paper describes the AVS architecture and presents an analysis of its expected performance.
Equipment Division of Raytheon Company has recently completed the design of a fault tolerant, tightly coupled multiprocessing computer system for an aerospace application. The system includes 11 modules consisting of 8 ASICs, 17 FPGAs, commercial off the shelf complex components, and off the shelf MSI and SSI devices. VHDL was used as the primary vehicle for modeling, simulation, and validation that has been integrated into Raytheon's existing design environment. This paper emphasizes the lessons learned in the process of developing and integrating this system. Topics to be covered include: migration to VHDL, design implementation, VHDL coding techniques, plus functional and timing verification tips through the use of hardware accelerators.
VHDL users at all levels of expertise rely on textbooks to enhance their coding techniques and to improve their understanding of this hardware description language. Unfortunately, many of these books contain, and hence perpetuate, a multitude of inefficient programming styles, false statements, and textual bloopers. Inefficient coding styles will needlessly slow down the model's simulation. False statements about VHDL will result in lengthy and frustrating debugging sessions. Textual bloopers will confuse and disorient the reader. This paper presents a wide range of examples from the VHDL literature that are potentially detrimental to the reader's growth as VHDL designers and engineers.
Logic synthesis and optimization derive their strength from assuming a restrictive model of the logic design world. When "tamed" and applied to parts of the chip design problem, they do significantly improve productivity. However, any design of reasonable complexity necessitates the application of "design knowledge" beyond the ability of logic synthesis and optimization. We have developed a set of VHDL packages called "VHDL Toolkit" that lead to a very expressive and technology transparent abstraction for design capture in VHDL. Here technology transparency does not merely mean the ability to target to the synthesizable subset of any cellset, but it includes 1) the ability of controlled mapping to other context specific efficient combinational and storage cells, 2) the ability to capture data flow for data path compilation to a layout technology that benefits from it. 3) the ability to capture asynchronous parts and "logic tricks". 4) the ability to partition out design parts that need to be implemented at the layout level and more. In this paper, we delineate the need for an expressive abstraction, illustrate the benefits with examples and discuss the language and the tool mechanisms that make such an abstraction possible.
The Equipment Division of Raytheon Company is striving to develop a VHDL based top-down design, bottom-up verification methodology. The goal of this methodology is to support and automate the process of transitioning complex digital systems from top level system specifications to hardware implementation. This paper will discuss the present state of that methodology, the tool suite required to support the methodology, and the successful application of the methodology to a major Department of Defense program. In addition, pathfinding efforts and associated tools for extending the methodology will be described. The first application of this methodology to a major program resulted in a 16 percent cost reduction and 30 percent schedule improvement over previous approaches. The program is a space-based, signal and data processing system which required eleven modules (8"x 8" double sided, surface mount), eight ASICs (10K - 60K gates), seventeen FPGAs, off the shelf complex components, and off the shelf MSI and SSI devices. This accomplishment was largely due to the initial efforts that were invested to pathfind and evaluate CAE tool options and the development of a concrete design methodology for all facets of system design.
This work presents a new approach to develop a concurrent hierarchical fault simulator using full VHDL. Our approach is based on the underlying model of VHDL. Faults are injected through VHDL perturbations of the elaborated model. Fault simulation is carried out on the sequential statements of the elaborated model, so a behavioral fault model can be used. Then, effects of faults can be followed and identified through the design hierarchy. This allows to compare models at different abstraction levels. Finally, the architecture of a concurrent and hierarchical fault simulator under development is presented.
This paper discusses some well known problems associated with shared variables and examines their relation to VHDL modelling, the emerging VHDL92 standard, and what a user can do to minimize the risks associated with using this powerful new feature.
This paper presents a new approach to the automatic generation of a synthesizable VHDL model for the multiple synthesizable subsets environment. Our approach is based on the idea of independent and user-definable synthesis rule set. Unlike the previous methods, the proposed method separates a synthesis rule set from the model generator. The rules are consulted and used as the base for inferring the algorithm/construct of the model during the model generation phase. By changing or creating the independent rule set, a designer is able to generate a synthesizable VHDL model for different synthesizable subsets. In the implementation of the proposed method, a set of engineering parameters is used as input data for the circuit description.
This paper presents a rule based environment for designing ASIC's using VHDL. The environment supports all levels of design entry from High Level behavior description through RTL and structural descriptions. The design is taken through simulation and synthesis to floorplanning and layout to create a working ASIC. The environment includes a VHDL simulator, VHDL behavioral synthesizer, logic and memory block generators, logic synthesizer & optimizer, synthesis manager and a task manager. Also included are links to timing analyzers, place and route tools and backannotation of delay information to the VHDL description for simulation.
An ability to model and simulate a Local Area Network (LAN), consisting of components that interact frequently and execute concurrently, is critical in predicting its dynamic behavior. An accurate prediction of LAN behavior is required in order to assess capacity requirements and implications for additions to the LAN. VHDL is well-suited for this purpose and has been successfully employed to model and analyze LAN performance for a commercial organization. We describe generic VHDL models that can be utilized to construct a LAN model. In addition, we demonstrate VHDL's effectiveness by comparing the results of a baseline LAN simulation with simulations of four LANs obtained through modifications to the operational load and configuration of the baseline.
Since its inception, VHDL has been promoted as a language for multi-level design. Proponents of the language have advocated its use partly on the grounds that it could accommodate design needs from high level requirements through RTL synthesis to gates, and gate level simulation. In recent years the language has enjoyed great success in satisfying design needs at high and intermediate levels of abstraction. VHDL is used extensively for simulation of behavioral and RTL descriptions. The language is also used for synthesis and optimization. For simulation at the gate level however, VHDL has not been as successful. Sign-off simulation, in particular, has traditionally been done using other languages. In this paper we present an approach to sign-off simulation of ASICs in VHDL.
This paper reports on an evaluation of commercial synthesis systems from Racal-Redac, Mentor Graphics and Synopsys. The tools have been evaluated with a circuit example from a previous, commercial ASIC design as reference. The conclusion is that automated synthesis from RTL VHDL to a final design is possible and feasible. Furthermore, the synthesized designs are of a quality comparable to what is seen in a gate-level design from a commercial project, and the design time is much shorter.
This paper describes our experiences using VHDL to develop a large behavioral model of Application Business System's next-generation hardware system architecture. The model addresses the need for a precise, operational definition of the system, analysis of design trade-offs, verification of design integrity, and potential for future hardware synthesis. These diverse needs lead to trade-offs in the level of abstraction, partitioning, and timing. Through this paper we attempt to convey the lessons which would have facilitated our effort and may yet benefit other architects.
This paper describes technology for optimized, native compiled code simulation of VHDL models using networked and parallel computers (MinSim). We describe the structure of the compiler and runtime system as well as several new optimization techniques.
VHDL provides the ability to use external industry standard CAD tools for chip design. Sometimes it is necessary to provide VHDL models with the original source code to CAD vendors to resolve tool bugs. In order to protect the intellectual property and prevent any disclosure of proprietary information, it is desirable to hide critical design information but still provide the source code to vendors for tool debug. VEP (VHDL Encryption Program) is a VHDL code encryption utility that has been developed to protect the confidentiality of design information. This tool uses a set of predefined rules to encrypt specific signals, variables and design unit names. The resulting model is still syntactically correct VHDL but has minimal design specific information. VEP has been used on over 7000 VHDL files for exchanging design data with tool vendors.
The VITAL Initiative was started to promote the availability of VHDL ASIC libraries by providing a solution to the timing/back-annotation problem for VHDL. This paper traces the history of VITAL and analyzed the strengths and weaknesses of the technical proposals which were considered during the design effort. The paper also describes and analyzes the current technical specification which is being handed off to the IEEE Timing Working Group for standardizations. The analysis focuses on the trade-offs made between flexibility, efficiency, timing accuracy, and industry acceptance. It then discusses the current status and plans for VITAL including the standardization effort and a program for building prototype VITAL libraries. The major issues dealt with were: 1. Modeling style and timing interface 2. Scope and definition of the underlying timing/delay model and constraints 3. Relationship of specification to related standards (VHDL-92, SDF...) The paper concludes with a description of the important points in the current Modeling specification with an example of how they are applied to ASIC library cells and a schema for back-annotating those models. The analysis of this example provides insight into their efficiency.
When a large VHDL model is being developped by several individuals, a set of guidelines is necessary to ensure maintainability, consistency and readability throughout. This paper presents a set of guidelines covering issues like file naming, capitalization and code layout, successfully used within BNR.
This paper describes a project undertaken by students in a computer architecture course at the University of Adelaide. The project involves using VHDL to model a computer system at the behavioral and register transfer levels, and making measurements during simulation to get quantitative data relevant to a computer architect. The project brings to light a number of positive aspects of VHDL when used for modelling at high levels of abstraction in this kind of environment.
We report on how timing constraints can be specified in VHDL for logic synthesis and high-level synthesis. Emphasis is placed on how to present timing constraints so that they can be simulated before synthesis. This helps the user to locate the critical portion of his/her design. Hence, performance constraints can be partitioned accordingly. To do so, a set of timing functions is constructed. They allow relativity, duration and event-cause to be described in various kinds of timing constraints, such as input/output timing constraints and relative timing constraints. Their usages and limitations are discussed.
This paper describes an experience in modeling of a large telecommunication switching system for architecture exploration. It examines the modeling techniques and methodology used. It also explores the issues of: 1) model writing for ease of verification; 2)model testbench creation; 3) monitoring the progression of a simulation. In this application an important aspect of the model was its flexibility for examining a variety of system configurations. The model developed supports significant reconfiguration without having to modify the VHDL model. An additional key aspect of the model is the ability of its testbench to "intelligently" extract relevant information out of the wealth of activity going on during simulation.
The goal in a design environment is to reduce cycle time by efficient reuse of previously generated circuitry. VHDL provides an efficient means to achieve these goals. RTL VHDL can be used to generate efficient logic designs in the ASIC environment. In some situations, reuse of design work may involve merging synthesized logic designs with circuitry previously designed "by hand." Care must be taken when generating the RTL VHDL to fully describe the interface between the synthesized gates and the existing logic design. Failure to fully describe this interface may result in unnecessary logic that may impact on the degree of testability of an ASIC design.
This paper discusses the use of the VHSIC Hardware Description Language (VHDL) to design three separate Application Specific Integrated Circuits (ASICs) for a single Multi-Chip Module (MCM). VHDL was selected in order to meet a customer requirement for deliverable VHDL models of ASIC devices. Synthesis was used to obtain gate level implementations from VHDL models. Originally, the ASIC designs were targeted for a field programmable gate array (FPGA) technology. Due to changes in the system performance requirements of the MCM, the FPGA technology became impractical. The technology independence of VHDL allowed the ASIC technology to be switched midcourse in the ASIC design process without significant impact on the development program schedule. One ASIC is being produced using a standard cell technology and two are being produced using a masked gate array technology. Three FPGAs of limited functionality were produced for rapid system prototyping.
As a standard modeling language, VHDL promises to reduce the cost of ASIC and standard component modeling while increasing the availability of high quality libraries. However, to fully realize its potential, VHDL must offer competitive performance. Although VHDL simulators continue to get faster, a significant performance and capacity gap still exists between VHDL and proprietary tools, particularly at the gate level. Multi-processor workstations provide a platform for accelerating VHDL simulation through the application of multi-threading. Given a pessimistic, time-synchronized implementation, the performance potential of a multi-threaded VHDL simulator is directly proportional to the degree of parallelism exhibited by a particular design executing a specific stimulus. One way to assess this potential is to instrument a VHDL simulator with the ability to generate statistics from which the parallelism of a design simulation can be determined. Several typical design simulations were executed on an instrumented version of the IKOS Voyager VS simulator. The results indicate the upper and lower bounds of the simulation performance that can be expected from a multi-threaded implementation employing a pessimistic concurrent algorithm.
Several design heuristics and methods have grown out of our experiences in using VHDL behavioral models as system design tools. This paper summarizes data gathered during model development and describes design methods developed to increase the utility of such models.
This presentation describes a hybrid design methodlogy of LSIs and MCM (Multichip Module) using VHDL as an example of NEC's experiences. This hybrid design methodolgy applies VHDL design methods only to function level design, and traditional design methods to gate level design. LSIs which are mentioned here are custom LSIs, and timing and function libraries for VHDL simulator are not supported yet. Futher, it is very difficult to synthesize their gate level circuits, because high performances are required at about 200MHz clock. Using this hybrid design method, these LSIs on MCM were developed in a short period. Three kinds of LSI and MCM were developed using VHDL concurrently. MCM is composed of 3 kinds of LSIs, 14 LSIs in total. LSIs are described as behavioral VHDL model, and a VHDL structural model of MCM corresponds to more than 1300K gates level circuits. This presentation will highlight our CAD environment and experiences to develop these LSIs and MCM. In conclusion, we will show our plan for developing methodologies using VHDL and requirements for EDA vendor.
A general queuing network-based simulation system useful for analyzing the performance and resource loading of computing systems has been developed which uses VHDL as the simulation engine. The system to be simulated is described as a extended queuing network in the simple PERFSIM language. A program, written in C++, converts the description into VHDL code which is then analyzed and executed to simulate the system. This paper describes the PERFSIM simulator and input language.
In this paper we present a system for automatic synthesis of special purpose hardware for neural networks. Only an algorithmic description of the behaviour of the hardware and a simulation environment have to be written by the designer using VHDL. This description can be automatically mapped onto hardware using the synthesis tool CALLAS and the design system MENTOR. Using the concept of a simulation block connected to the actual design level of the hardware implementation the consistency of the different design levels can be proved. By using reprogrammable gate arrays (FPGAs) with this system we are able to do rapid prototyping of neural network hardware in a few days.
Approaches to teaching VHDL at the undergraduate and graduate levels are given. An undergraduate course gives an introduction to VHDL and teaches high level design synthesis in a PC based schematic capture environment. A graduate course teaches the detailed syntax and semantics of the VHDL language and fully explores its modeling capabilities. Laboratory support and experiments are described for each course. Conclusions based on teaching experience are drawn.
After two small pilot projects using the VHDL language in a top-down design methodology, Amdahl began its first major project in VHDL. Since the project was staffed with experienced engineers with limited VHDL exposure, and VHDL is a complex language, training was on the critical path. Amdahl embarked on the systematic training of a large and diverse development team in a period of several weeks. This paper will describe the process from start to finish, covering the need for training, course content, instructor selection, and post-training support. Key successes and lessons learned will be highlighted as well.